AD7674

Data Sheet

Rev. B | Page 10 of 28

Pin No.

Mnemonic

Description

32

CS

DI

Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is

also used to gate the external clock.

33

RESET

DI

Reset Input. When set to a logic high, reset the AD7674. Current conversion, if any, is aborted. If not

used, this pin can be tied to DGND.

34

PD

DI

Power-Down Input. When set to a logic high, power consumption is reduced and conversions are

inhibited after the current one is completed.

35

CNVST

DI

Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold state and

initiates a conversion. In impulse mode (IMPULSE high, WARP low), if CNVST is held low when the

immediately started.

36

AGND

P

Must Be Tied to Analog Ground.

37

REF

AI

Reference Input Voltage and Internal Reference Buffer Output. Apply an external reference on REF if

the internal reference buffer is not used. Should be decoupled effectively with or without the internal

buffer.

38

REFGND

AI

Reference Input Analog Ground.

39

IN–

AI

Differential Negative Analog Input.

40 to

42

NIC

No Internal Connection.

43

IN+

AI

Differential Positive Analog Input.

45

DNC

Do Not Connect. Do not connect to this pin.

46

REFBUFIN

AI

Reference Buffer Input Voltage. The internal reference buffer has a fixed gain. It outputs 4.096 V

typically when 2.5 V is applied on this pin.

48

PDBUF

DI

Allows Choice of Buffering Reference. When low, buffer is selected. When high, buffer is switched off.

0

EPAD

Exposed Pad. The exposed pad is internally connected to AGND. This connection is not required to

meet the electrical performances. However, for increased reliability of the solder joints, it is

recommended that the pad be soldered to the analog ground of the system.

Mode

MODE1

MODE0

D0/OB/2C

D1/A0

D2/A1

D[3]

D[4:9]

D[10:11]

D[12:15]

D[16:17]

Description

0

0

0

R[0]

R[1]

R[2]

R[3]

R[4:9]

R[10:11]

R[12:15]

R[16:17]

18-bit parallel

1

0

1

OB/2C

A0:0

R[2]

R[3]

R[4:9]

R[10:11]

R[12:15]

R[16:17]

16-bit high word

1

0

1

OB/2C

A0:1

R[0]

R[1]

All zeros

16-bit low word

2

1

0

OB/2C

A0:0

A1:0

All high-Z

R[10:11]

R[12:15]

R[16:17]

8-bit high byte

2

1

0

OB/2C

A0:0

A1:1

All high-Z

R[2:3]

R[4:7]

R[8:9]

8-bit mid byte

2

1

0

OB/2C

A0:1

A1:0

All high-Z

R[0:1]

All zeros

8-bit low byte

2

1

0

OB/2C

A0:1

A1:1

All high-Z

All zeros

R[0:1]

8-bit low byte

3

1

1

OB/2C

All high-Z

Serial interface

Serial interface