AD7732 datasheet(13/33 Pages) AD

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AD7732

Rev. A | Page 12 of 32

PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS

TOP VIEW

(Not to Scale)

AD7732

BIAS0(+)

AIN0(+)

AIN1(+)

BIAS1(+)

SYNC/P1

SCLK

MCLKIN

AVDD

RESET

BIAS0(–)

AIN0(–)

AIN1(–)

BIAS1(–)

REFIN(+)

DGND

DVDD

DIN

DOUT

REFIN(–)

AGND

RDY

MCLKOUT

Figure 11. 28-Lead TSSOP

SYNC/P1

AIN0(+)

AIN1(+)

AIN0(–)

BIAS0(+)

BIAS0(–)

AIN1(–)

BIAS1(+)

BIAS1(–)

SCLK

DIN

DOUT

RESET

RDY

DGND

MCLKIN

MCLKOUT

AGND AVDD

DVDD

AVDD

DVDD

R=15.5k

BUFFER

REFERENCE

DETECT

REFIN(–)

REFIN(+)

AD7732

24-BIT

Σ−Δ ADC

SERIAL

INTERFACE

CONTROL

LOGIC

CLOCK

GENERATOR

CALIBRATION

CIRCUITRY

I/O PORT

MUX

Figure 12. Block Diagram

Table 10. Pin Function Descriptions—28-Lead TSSOP

Pin No.

Mnemonic

Description

SCLK

Serial Clock. Schmitt triggered logic input. An external serial clock is applied to this input

to transfer serial data to or from the AD7732.

MCLKIN

Master Clock Signal for the ADC. This can be provided in the form of a crystal/resonator

or external clock. A crystal/resonator can be tied across the MCLKIN and MCLKOUT pins.

Alternatively, the MCLKIN pin can be driven with a CMOS compatible clock and

MCLKOUT left unconnected.

MCLKOUT

When the master clock for the device is a crystal/resonator, the crystal/resonator is

connected between MCLKIN and MCLKOUT. If an external clock is applied to the

MCLKIN, MCLKOUT provides an inverted clock signal or can be switched off to reduce

the device power consumption. MCLK OUT is capable of driving one CMOS load.

Chip Select. Active low Schmitt triggered logic input with an internal pull-up resistor.

With this input hardwired low, the AD7732 can operate in its 3-wire interface mode

using SCLK, DIN, and DOUT. CS can be used to select the device in systems with more

than one device on the serial bus. It can also be used as an 8-bit frame

synchronization signal.

RESET

Schmitt Triggered Logic Input. Active low input that resets the control logic, interface

logic, digital filter, analog modulator, and all on-chip registers of the part to power-on

status. Effectively, everything on the part except the clock oscillator is reset when the

RESET pin is exercised.

AVDD

Analog Positive Supply Voltage. 5 V to AGND nominal.

Digital Input/Output. The pin direction is determined by the P0 DIR bit; the digital

value can be read/written as the P0 bit in the I/O port register. The digital voltage is

referenced to analog supplies. When configured as an input, the pin should be tied

high or low.

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