AD7732

Rev. A | Page 15 of 32

Register Access

The AD7732 is configurable through a series of registers. Some

of them configure and control general AD7732 features, while

others are specific to each channel. The register data widths

vary from 8 bits to 24 bits. All registers are accessed through the

communications register, i.e., any communication to the

AD7732 must start with a write to the communications register

specifying which register will be subsequently read or written.

Communications Register

8 Bits, Write-Only Register, Address 00h

All communications to the part must start with a write

operation to the communications register. The data written to

the communications register determines whether the

subsequent operation will be a read or write and to which

register this operation will be directed. The digital interface

defaults to expect write operation to the communications

register after power-on, after reset, or after the subsequent read

or write operation to the selected register is complete. If the

interface sequence is lost, the part can be reset by writing at

least 32 serial clock cycles with DIN high and CS low. (Note that

all of the parts, including the modulator, filter, interface, and all

registers are reset in this case.) Remember to keep DIN low

while reading 32 bits or more either in continuous read mode or

with the DUMP bit and “24/16” bit in the mode register set.

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Mnemonic

0

R/W

6-Bit Register Address

Bit

Mnemonic

Description

7

0

This bit must be 0 for proper operation.

6

R/W

A 0 in this bit indicates that the next operation will be a write to a specified register. A 1 in this bit indicates

that the next operation will be a read from a specified register.

5–0

Address

Address specifying to which register the read or write operation will be directed. For channel specific registers,

Bit 1 specifies the channel number. When the subsequent operation writes to the Mode register, Bit 1 specifies

the channel selected for operation determined by the mode register value (see Table 14).

Table 14.

Bit 2

Bit 1

Bit 0

Channel

Input

0

0

0

0

AIN0(+) – AIN0(–)

0

1

0

1

AIN1(+) – AIN1(–)