AD7732

Rev. A | Page 20 of 32

Mode Register

8 Bits, Read/Write Register, Address 38h, 3Ah, Default Value 00h

The mode register configures the part and determines its operating mode. Writing to the mode register clears the ADC status register, sets

the RDY pin to a logic high level, exits all current operations, and starts the mode specified by the mode bits.

The AD7732 contains only one mode register. Bit 1 of the address is used for writing to the mode register to specify the channel selected

for the operation determined by the MD2 to MD0 bits. Only the address 38h must be used for reading from the mode register.

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Mnemonic

MD2

MD1

MD0

CLKDIS

DUMP

Cont RD

24/16 BIT

CLAMP

Default

0

0

0

0

0

0

0

0

Bit

Mnemonic

Description

7–5

MD2–MD0

Mode Bits. These three bits determine the AD7732 operation mode. Writing a new value to the mode bits will

exit the part from the mode in which it has been operating and place it in the newly requested mode

immediately. The function of the mode bits is described in more detail below.

4

CLKDIS

Master Clock Output Disable. When this bit is set to 1, the master clock is disabled from appearing at the

MCLKOUT pin and the MCLKOUT pin is in a high impedance state. This allows turning off the MCLKOUT as a

power saving feature. When using an external clock on MCLKIN, the AD7732 continues to have internal clocks

and will convert normally regardless of the CLKDIS bit state. When using a crystal oscillator or ceramic

resonator across the MCLKIN and MCLKOUT pins, the AD7732 clock is stopped and no conversions can take

place when the CLKDIS bit is active. The AD7732 digital interface can still be accessed using the SCLK pin.

3

DUMP

DUMP Mode. When this bit is reset to 0, the channel status register and channel data register will be

addressed and read separately. When the DUMP bit is set to 1, the channel status register will be followed

immediately by a read of the channel data register regardless of whether the status or data register has been

addressed through the communication register. The continuous read mode will always be dump mode

reading of the channel status and data register, regardless of the dump bit value (see the Digital Interface

Description section for more details).

2

Cont RD

When this bit is set to 1, the AD7732 will operate in the continuous read mode (see the Digital Interface

Description section for more details).

1

24/16 BIT

The Channel Data Register Data Width Selection Bit. When set to 1, the channel data registers will be 24 bits

wide. When set to 0, the channel data registers will be 16 bits wide.

0

CLAMP

This bit determines the channel data register’s value when the analog input voltage is outside the nominal

input voltage range. When the CLAMP bit is set to 1, the channel data register will be digitally clamped either

to all 0s or all 1s when the analog input voltage goes outside the nominal input voltage range. When the

CLAMP bit is reset to 0, the data registers reflect the analog input voltage even outside the nominal voltage

range (see the Analog Input’s Extended Voltage Range section).

MD2

MD1

MD0

Mode

Address Used for Mode Register Write Specifies:

0

0

0

Idle Mode

0

0

1

Continuous Conversion Mode

The First Channel to Start Converting

0

1

0

Single Conversion Mode

Channel to Convert

0

1

1

Power-Down (Standby) Mode

1

0

0

ADC Zero-Scale Self-Calibration

Channel Conversion Time Used for the ADC Self-Calibration

1

0

1

For Future Use

1

1

0

Channel Zero-Scale System Calibration

Channel to Calibrate

1

1

1

Channel Full-Scale System Calibration

Channel to Calibrate