MRF89XA datasheet(33/140 Pages) MICROCHIP

33 / 140 page

 2010-2017 Microchip Technology Inc.

Preliminary

DS70000622D-page 33

MRF89XA

2.14.5

FLOOR THRESHOLD CONTROL REGISTER DETAILS

FLTHREG: FLOOR THRESHOLD CONTROL REGISTER

(ADDRESS:0x04) (POR:0x0C)

2.14.6

FIFO CONFIGURATION REGISTER DETAILS

FIFOCREG: FIFO CONFIGURATION REGISTER (ADDRESS:0x05) (POR:0x0F)

R/W-0

R/W-1

R/W-0

FTOVAL<7:0>

bit 7

bit 0

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

r = Reserved

bit 7-0

FTOVAL<7:0>: Floor Threshold OOK Value bits

The bits indicate Floor threshold in OOK receive mode.

FTOVAL<7:0> = 00001100  6 dB (default)

FTOVAL assumes 0.5 dB RSSI Step

R/W-0

R/W-1

FSIZE<1:0>

FTINT<5:0>

bit 7

bit 0

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

r = Reserved

bit 7-6

FSIZE<1:0>: FIFO Size Selection bits

These bits set the size or number of FIFO locations.

11 = 64 bytes

10 = 48 bytes

01 = 32 bytes

00 = 16 bytes (default)

bit 5-0

FTINT<5:0>: FIFO Threshold Interrupt bits

Setting these bits selects the FIFO threshold for interrupt source. Refer to Section 3.6.2, Interrupt

Sources and Flags for more information.

FTINT<5:0> = 001111 (default)

The behavior of the FIFO_THRESHOLD interrupt source depends on the running mode (TX, RX, or

Standby mode).

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