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MRF89XA Datasheet(PDF) 41 Page - Microchip Technology |
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MRF89XA Datasheet(HTML) 41 Page - Microchip Technology |
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41 / 140 page  2010-2017 Microchip Technology Inc. Preliminary DS70000622D-page 41 MRF89XA 2.15.3 RSSI THRESHOLD INTERRUPT REQUEST REGISTER DETAILS REGISTER 2-16: RSTHIREG: RSSI THRESHOLD INTERRUPT REQUEST CONFIGURATION REGISTER (ADDRESS:0x0F) (POR:0x00) bit 0 LENPLL: Lock Enable of PLL bit 1 = PLL lock detect enabled (default) 0 = PLL lock detect disabled The PLL lock detect flag is mapped to the PLOCK pin (pin 23), and pin 23 is a High-Z pin. R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RTIVAL<7:0> bit 7 bit 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown r = Reserved bit 7-0 RTIVAL<7:0>: RSSI Threshold for Interrupt Value bits These bits indicate the RSSI threshold value for interrupt request. RTIVAL<7:0> = 00000000 (default) REGISTER 2-15: FTPRIREG: FIFO TRANSMIT PLL AND RSSI INTERRUPT REQUEST CONFIGURATION REGISTER (ADDRESS:0x0E) (POR:0x01) (CONTINUED) |
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