AD9670EBZ datasheet(28/53 Pages) AD

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Data Sheet

AD9670

Rev. A | Page 27 of 52

Tuning is normally off to avoid changing the capacitor settings

during critical times. The tuning circuit is enabled through the

SPI. It is disabled automatically after 512 cycles of the ADC sample

clock. Initializing the tuning of the filter must be performed after

initial power-up and after reprogramming the filter cutoff

scaling or ADC sample rate. The tuning is initiated in

A total of four SPI-programmable settings allow the user to vary

the high-pass filter cutoff frequency as a function of the low-

pass cutoff frequency. Two examples are shown in Table 13: one

example is for an 8 MHz low-pass cutoff frequency, and the other

example is for an 18 MHz low-pass cutoff frequency. In both

examples, as the ratio decreases, the amount of rejection on the

low-end frequencies increases. Therefore, making the entire

antialiasing filter frequency pass band narrow can reduce low

frequency noise or maximize dynamic range for harmonic

processing.

Table 13. High-Pass Filter Cutoff Options

Reg. 0x02B[1:0]

High-Pass Filter

Cutoff

High-Pass Cutoff Frequency

Ratio1

Low-Pass

Cutoff = 8 MHz

Low-Pass

Cutoff = 18 MHz

00 (default)

12.00

670 kHz

1.5 MHz

9.00

890 kHz

2.0 MHz

6.00

1.33 MHz

3.0 MHz

3.00

2.67 MHz

6.0 MHz

1 Ratio is the low-pass filter cutoff frequency/high-pass filter cutoff frequency.

Antialiasing Filter/VGA Test Mode

For debug and testing, there is a bypass switch to view the anti-

aliasing filter output on the GPO2 and GPO3 pins. Enable this

mode using SPI Register 0x109, Bit 4. The differential antialiasing

filter output of only one channel can be accessed at a time. The

dc output voltage is 1.5 V (or AVDD2/2) and the maximum ac

output voltage is 2 V p-p.

ADC

The AD9670 uses a pipelined ADC architecture. The quantized

output from each stage is combined into a 14-bit result in the

digital correction logic. The pipelined architecture permits the

first stage to operate on a new input sample and the remaining

stages to operate on preceding samples. Sampling occurs on the

rising edge of the clock.

The output staging block aligns the data, corrects errors, and

passes the data to the output buffers. The data is then serialized

and aligned to the frame and output clocks.

Clock Input Considerations

For optimum performance, clock the AD9670 sample clock

inputs (CLK+ and CLK−) with a differential signal. This signal

is typically ac-coupled into the CLK+ and CLK− pins via a trans-

former or capacitors. These pins are biased internally and require

no additional bias.

Figure 39 shows the preferred method for clocking the AD9670. A

low jitter clock source, such as the Valpey Fisher oscillator, VFAC3-

BHL-50 MHz, is converted from single-ended to differential using

an RF transformer. The back to back Schottky diodes across the

secondary transformer limit clock excursions into the AD9670

to approximately 0.8 V p-p differential. This helps prevent the

large voltage swings of the clock from feeding through to other

portions of the AD9670, and it preserves the fast rise and fall

times of the signal, which are critical to low jitter performance.

0.1µF

SCHOTTKY

DIODES:

HSM2812

3.3V

50Ω 100Ω

CLK–

CLK+

AD9670

MINI-CIRCUITS®

ADT1-1WT, 1:1Z

XFMR

VFAC3

OUT

Figure 39. Transformer-Coupled Differential Clock

If a low jitter clock is available, another option is to ac-couple

a differential PECL signal to the sample clock input pins, as

shown in Figure 40. Analog Devices, Inc., offers a family of

clock drivers with excellent jitter performance, including the

AD9516-0, AD9516-1, AD9516-2, AD9516-3, and AD9516-5

(these five devices are represented by AD9516-x in Figure 40,

Figure 41, and Figure 42), as well as the AD9524.

100Ω

0.1µF

240Ω

AD9516-x

OR AD9524

CLK

*50Ω RESISTOR IS OPTIONAL.

PECL DRIVER

3.3V

OUT

VFAC3

CLK–

CLK+

AD9670

50Ω*

Figure 40. Differential PECL Sample Clock

A third option is to ac couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 41.

100Ω

0.1µF

AD9516-x

OR AD9524

CLK

*50Ω RESISTOR IS OPTIONAL.

LVDS DRIVER

3.3V

OUT

VFAC3

CLK–

CLK+

AD9670

50Ω*

Figure 41. Differential LVDS Sample Clock

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