AD9670EBZ datasheet(36/53 Pages) AD

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AD9670

Data Sheet

Rev. A | Page 35 of 52

DIGITAL DEMODULATOR/DECIMATOR

The AD9670 contains digital processing capability. Each channel

has three stages of processing available: the RF decimator, the

baseband demodulator, and the baseband decimator. For test

purposes, the input to the demodulator/decimator can be a test

waveform. Normally, this input is the output of the ADC. The

output of the demodulator/decimator is sent to the framer/

serializer for output formatting.

The maximum data rate of the baseband demodulator and

decimator is 65 MSPS. Therefore, if the sample of the ADC is

greater than 65 MSPS, the RF decimator (with a fixed rate of 2)

must be enabled. The ADC resolution is 14 bits. The maximum

resolution at the output of the digital processing is 16 bits. Sat-

uration of the ADC is determined after the dc offset calibration to

ensure maximum dynamic range. Depending on the decimation

rate, the loss in output SNR due to truncation to 16 bits is

negligible.

VECTOR PROFILE

To minimize time needed to reconfigure device settings during

operation, the device supports configuration profiles. Up to

32 profiles can be stored in the device. A profile is selected by a

5-bit index. A profile consists of a 64-bit vector, as described in

Table 21. Each parameter is concatenated to form the 64-bit

profile vector. The profile memory starts at Register 0xF00 and

ends at Register 0xFFF. The memory can be written in either

stream or address selected data mode. However, the memory

must be read using stream mode. When writing or reading in

stream mode while the SPI configuration is set to MSB first

mode (the default setting for Register 0x000), the write/read

address must refer to the last register address, not the first. For

example, when writing or reading the first profile that spans the

address space between Register 0xF00 and Register 0xF07, with

the SPI port configured as MSB first, the referenced address

must be Register 0xF07 to allow reading or writing the 64

profile bits in MSB mode. For more information, see the AN-877

Application Note, Interfacing to High Speed ADCs via SPI.

A buffer stores the current profile data. When the profile index

is written in Register 0x10C, the selected profile is read from

memory and stored in the current profile buffer. The profile

memory is read/written in the SPI clock domain. After the SPI

writes the profile index value, the SPI takes 4 SPI clock cycles to

read the profile from RAM and store it in the current profile

buffer. If the SPI is in LSB mode, these additional SPI clock

cycles are provided when the profile index register is written. If

the SPI is in MSB mode, an additional byte must be read or

written to update the profile buffer.

Updating the profile memory does not affect the data in the

profile buffer. The profile index register must be written to

cause a refresh of the current profile data, even if the profile

index register is written with the same value.

ADC OUTPUT OR

TEST WAVEFORM

DC OFFSET

CALIBRATION

MULTIBAND AAF

DECIMATE BY 2

NUMERICALLY

CONTROLLED

OSCILLATOR

RF DECIMATOR

FRAMER

SERIALIZER

HIGH-PASS

FILTER

–Sin

Cos

BB DECIMATOR

BB DEMODULATOR

LOW-PASS

FILTER

DECIMATOR

LOW-PASS

FILTER

DECIMATOR

Figure 49. Simplified Block Diagram of a Single Channel of the Demodulator/Decimator

Table 21. Profile Definition

Field

Bits

Description

Demodulation frequency (fD)

fD = f × fSAMPLE/216, where f = [0,(216 − 1)] and fSAMPLE is the effective sample rate

0x0000: fD = 0 (dc, I = cos(0) = 1, Q = sin(0) = 0)

0x0001: fD = fSAMPLE/216

…

0x8000: fD = fSAMPLE/2

…

0xFFFF (216 − 1): fD = fSAMPLE (216 − 1)/ 216 =−fSAMPLE/216

Pointer to coefficient block; the coefficients used begin at coefficient P × 8 and continue for M × 8 coefficients, for

example,

0000 0000: points to coefficient 0 and continues M × 8 coefficients

0000 0001: points to coefficient 8 and continues M × 8 coefficients

AD9670EBZ Datasheet(PDF) 36 Page - Analog Devices

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