AD9670EBZ datasheet(31/53 Pages) AD

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AD9670

Data Sheet

Rev. A | Page 30 of 52

An example of the LVDS output using the ANSI-644 standard

(default) data eye and a time interval error (TIE) jitter histogram

with trace lengths of less than 24 inches on regular FR-4 material is

shown in Figure 45 and Figure 46. Figure 47 and Figure 48 show

examples of the trace lengths exceeding 24 inches on regular

FR-4 material. Notice that the TIE jitter histogram reflects the

decrease of the data eye opening as the edge deviates from the

ideal position; therefore, the user must determine whether the

waveforms meet the timing budget of the design when the trace

lengths exceed 24 inches.

400

–200

200

300

–100

100

–400

–300

–1.5

–0.5

–1.0

0.5

1.0

1.5

TIME (ns)

EYE: ALL BITS

ULS: 11197/11197

Figure 45. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths

of Less Than 24 Inches on Standard FR-4 Material

–150

–100

–50

TIME (ps)

100

150

Figure 46. TIE Jitter Histogram for LVDS Outputs in ANSI-644 Mode with

Trace Lengths of Less Than 24 Inches on Standard FR-4 Material

400

–200

–300

200

300

–100

100

–400

–1.5

–0.5

–1.0

TIME (ns)

0.5

1.0

1.5

ULS: 11199/11199

EYE: ALL BITS

Figure 47. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of

Greater Than 24 Inches on Standard FR-4 Material

TIME (ps)

–300

–200

–100

200

100

300

Figure 48. TIE Jitter Histogram for LVDS Outputs in ANSI-644 Mode with

Trace Lengths of Greater Than 24 Inches on Standard FR-4 Material

Additional SPI options allow the user to further increase the

internal current of all eight outputs to drive longer trace lengths.

Even though this produces sharper rise and fall times on the

data edges, it is less prone to bit errors and improves frequency

distribution. The power dissipation of the DRVDD supply

increases when this option is used.

In cases that require increased drive current, Register 0x015

allows the user to adjust the drivers from 2.0 mA to 3.72 mA.

Note that this feature requires Bit 3 of Register 0x015 to be

enabled. The drive current can be adjusted for both ANSI-644

and IEEE (low power) mode. See Table 27 for more details.

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