AD9670EBZ datasheet(7/53 Pages) AD

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AD9670

Data Sheet

Rev. A | Page 6 of 52

Parameter1

Test Conditions/Comments

Min

Typ

Max

Unit

Two-Tone Intermodulation

Distortion (IMD3)

fRF1 = 5.015 MHz, fRF2 = 5.020 MHz, fLO = 80 MHz,

ARF1 = −1 dBFS, ARF2 = −21 dBFS, IMD3 relative to ARF2

−58

LO Harmonic Rejection

16LO, 8LO, and 4LO modes

−20

dBc

Quadrature Phase Error

I to Q, all phases, 1 σ

0.15

Degrees

I/Q Amplitude Imbalance

I to Q, all phases, 1 σ

0.015

Channel-to-Channel Matching

Phase I to I, Q to Q, 1 σ

0.5

Degrees

Amplitude I to I, Q to Q, 1 σ

0.25

POWER SUPPLY, MODE I/MODE II/

MODE III/MODE IV

AVDD1

1.7

1.8

1.9

AVDD2

2.85

3.0

3.6

DVDD

Demodulator/decimator enabled

1.3

1.4

1.9

Demodulator/decimator disabled

1.3

1.8

1.9

DRVDD

1.7

1.8

1.9

IAVDD1

TGC mode, LO band mode

148/187/

223/291

CW Doppler mode

IAVDD2

TGC mode, no signal, low band mode

230

TGC mode, no signal, high band mode

239

CW Doppler mode, 8 channels enabled

140

IDVDD

RF decimator enabled in Mode III and Mode IV;

demodulator/decimator enabled all modes

156/247/

166/255

IDRVDD

ANSI-644 mode

133/184/

141/146

Low power (IEEE 1596.3 similar) mode, 1 channel per

lane mode

119/170/

127/169

Total Power Dissipation

(Including Output Drivers)

TGC mode, no signal, RF decimator enabled in Mode III

and Mode IV, demodulator/decimator disabled

1200/1400/

1380/1630

1345/1555/

1535/2100

TGC mode, no signal, RF decimator enabled in Mode III

and Mode IV, demodulator/decimator enabled

1400/1695/

1570/1900

1560/1880/

1740/2100

CW Doppler mode, 8 channels enabled

500

Power-Down Dissipation

Standby Power Dissipation

630

ADC RESOLUTION

Bits

ADC REFERENCE

Output Voltage Error

VREF = 1 V

±50

Load Regulation at 1.0 mA

VREF = 1 V

Input Resistance

7.5

kΩ

1 For a complete set of definitions and information about how these tests were completed, see the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation.

2 The overrange condition is specified as 6 dB more than the full-scale input range.

3 The internal LO frequency, fLO, is generated from the supplied multiplier local oscillator frequency, fMLO, by dividing it up by a configurable divider value (M) that can be

4, 8, or 16; the MLO signal is named 4LO, 8LO, or 16LO, accordingly.

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