AD9670EBZ datasheet(30/53 Pages) AD

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Data Sheet

AD9670

Rev. A | Page 29 of 52

higher value decoupling capacitors on the GAIN± pins result in

longer wake-up times.

A number of other power-down options are available when using

the SPI port interface. The user can individually power down

each channel or put the entire device into standby mode. This

allows the user to keep the internal PLL powered up when fast

wake-up times are required. The wake-up time is slightly depend-

ent on gain. To achieve a 2 μs wake-up time when the device is

in standby mode, 0.8 V must be applied to the GAIN± pins.

Power and Ground Connection Recommendations

When connecting power to the AD9670, it is recommended that

two separate 1.8 V supplies be used: one for analog supply

(AVDD1) and one for digital supply (DRVDD). If only one

1.8 V supply is available, route this supply to the AVDD1 pin

first, and then tap the supply off and isolate it with a ferrite

bead or a filter choke preceded by decoupling capacitors for

the DRVDD pin.

If the user does not use the digital demodulator and decimator

functions for post ADC processing, the DVDD pin can be tied

to the 1.8 V DRVDD supply. If this is the case, route the DVDD

supply first, tapped the supply off, and isolated it with a ferrite

bead or filter choke preceded by decoupling capacitors for the

DRVDD pin. It is not recommended to use the same supply for

AVDD1, DVDD, and DRVDD.

Use several decoupling capacitors on all supplies to cover both

high and low frequencies. Locate these capacitors close to the

point of entry at the PCB level and close to the device, with

minimal trace lengths.

A single PCB ground plane is sufficient when using the AD9670.

With proper decoupling and smart partitioning of the analog,

digital, and clock sections of the PCB, optimum performance

is easily achieved.

Advanced Power Control

Not all channels are required during all periods of scanning in

an ultrasound system. Use the POWER_START and POWER_

STOP values in the vector profile to delay the channel startup

and to turn the channel off after a certain number of samples.

These counters are relative to TX_TRIG±. The analog circuitry

must power up before the digital circuitry, and the advance time

(POWER_SETUP) for powering up the analog circuitry, before

POWER_START, is set up in Register 0x112, Bits[4:0] (see

Table 27).

TX_TRIG±

POWER_STOP

(PROFILE SPECIFIC)

POWER_START

(PROFILE SPECIFIC)

POWER_SETUP

(SPI SET)

DIGITAL

POWER

ANALOG

POWER

Figure 44. Power Sequencing

Digital Outputs and Timing

The AD9670 differential outputs conform to the ANSI-644

LVDS standard on default power-up. This standard can be

changed to a low power, reduced signal option similar to the

IEEE 1596.3 standard via the SPI using Register 0x015, Bit 7.

This LVDS standard can further reduce the overall power

dissipation of the device by approximately 36 mW.

The LVDS driver current is derived on chip and sets the output

current at each output equal to a nominal 3.5 mA. A 100 Ω

differential termination resistor placed at the LVDS receiver

inputs results in a nominal 350 mV swing at the receiver.

The AD9670 LVDS outputs facilitate interfacing with LVDS

receivers in custom ASICs and FPGAs that have LVDS capability

for superior switching performance in noisy environments. Single

point-to-point network topologies are recommended with a

100 Ω termination resistor placed as close to the receiver as

possible. No far-end receiver termination and poor differential

trace routing may result in timing errors. The trace length must

be no longer than 24 inches. Keep the differential output traces

close together and at equal lengths.

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