80386EX datasheet(14/56 Pages) INTEL

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Intel386™ EX Embedded Microprocessor

Datasheet

D15:0

I/O

H(Z)

R(Z)

P(Z)

Data Bus inputs data during memory read, I/O read, and

interrupt acknowledge cycles and outputs data during memory

and I/O write cycles. During writes, this bus is driven during

phase 2 of T1 and remains active until phase 2 of the next T1,

T1P, or Ti. During reads, data is latched on the falling edge of

phase 2.

DACK1:0#

H(1)

R(1)

I(Q)

P(X)

DMA Acknowledge 1 and 0 signal to an external device that the

processor has acknowledged the corresponding DMA request

and is relinquishing the bus. DACK1# is multiplexed with TXD1,

and DACK0# is multiplexed with CS5#.

D/C#

H(Z)

R(1)

I(0)

P(0)

Data/Control indicates whether the current bus cycle is a data

cycle (memory or I/O read or write) or a control cycle (interrupt

acknowledge, halt, or code fetch).

DCD1:0

Data Carrier Detect SIO1 and SIO0 indicate that the modem or

data set has detected the corresponding asynchronous serial

channel’s data carrier. DCD1# is multiplexed with DRQ0, and

DCD0# is multiplexed with P1.0 and has a temporary weak pull-

up resistor.

DRQ1:0

DMA External Request 1 and 0 indicate that a peripheral

requires DMA service. DRQ1 is multiplexed with RXD1, and

DRQ0 is multiplexed with DCD1#.

DSR1:0#

Data Set Ready SIO1 and SIO0 indicate that the modem or data

set is ready to establish a communication link with the

corresponding asynchronous serial channel. DSR1# is

multiplexed with STXCLK and has a permanent weak pull-up

resistor, and DSR0# is multiplexed with P1.3 and has a

temporary weak pull-up resistor.

DTR1:0#

H(X)

R(WH)

I(X)

P(X)

Data Terminal Ready SIO1 and SIO0 indicate that the

corresponding asynchronous serial channel is ready to establish

a communication link with the modem or data set. DTR1# is

multiplexed with SRXCLK, and DTR0# is multiplexed with P1.2.

EOP#

I/OD

H(Z)

R(WH)

I(Z)

P(Z)

End of Process indicates that the processor has reached

terminal count during a DMA transfer. An external device can

also pull this pin LOW. EOP# is multiplexed with CTS1#.

ERROR#

Error indicates that the math coprocessor has an error condition.

ERROR# is multiplexed with TMROUT2 and has a temporary

weak pull-up resistor.

FLT#

Float forces all bidirectional and output signals except TDO to a

high-impedance state. It has a permanent weak pull-up resistor.

This pin should be tied to VCC through a 3 to 7 KOhm pull-up

resistor.

HLDA

H(1)

R(WL)

I(Q)

P(X)

Bus Hold Acknowledge indicates that the processor has

surrendered control of its local bus to another bus master. HLDA

is multiplexed with P1.7.

HOLD

Bus Hold Request allows another bus master to request control

of the local bus. HLDA active indicates that bus control has been

granted. HOLD is multiplexed with P1.6. It has a temporary weak

pull-down resistor.

Table 4.

Intel386™ EX Microprocessor Pin Descriptions (Sheet 2 of 6)

Symbol

Type

Output States

Name and Function

NOTES:

1. X if clock source is internal; Q if clock source is external

2. Q if JTAG unit is shifting out data, Z if it is not

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