80386EX datasheet(21/56 Pages) INTEL

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Intel386™ EX Embedded Microprocessor

Datasheet

Each asynchronous serial channel includes full modem control support (CTS#, RTS#, DSR#,

DTR#, RI#, and DCD#) and is completely programmable. The programmable options include

character length (5, 6, 7, or 8 bits), stop bits (1, 1.5, or 2), and parity (even, odd, forced, or none). In

addition, it contains a programmable baud-rate generator capable of clock rates from 0 to 512

Kbaud.

4.7

Synchronous Serial I/O Unit

The Synchronous Serial I/O (SSIO) unit provides for simultaneous, bidirectional communications.

It consists of a transmit channel, a receive channel, and a dedicated baud-rate generator. The

transmit and receive channels can be operated independently (with different clocks) to provide

non-lockstep, full-duplex communications; either channel can originate the clocking signal (Master

Mode) or receive an externally generated clocking signal (Slave Mode).

The SSIO provides numerous features for ease and flexibility of operation. With a maximum clock

input of CLK2/4 to the baud-rate generator, the SSIO can deliver a baud rate of up to 8.25 Mbits

per second with a processor clock of 33 MHz. Each channel is double buffered. The two channels

share the baud-rate generator and a multiply-by-two transmit and receive clock. The SSIO supports

16-bit serial communications with independently enabled transmit and receive functions and gated

interrupt outputs to the interrupt controller.

4.8

Parallel I/O Unit

The Intel386 EX microprocessor has three 8-bit, general-purpose I/O ports. All port pins are

bidirectional, with TTL-level inputs and CMOS-level outputs. All pins have both a standard

operating mode and a peripheral mode (a multiplexed function), and all have similar sets of control

registers located in I/O address space.

4.9

DMA and Bus Arbiter Unit

The Intel386 EX microprocessor’s DMA controller is a two-channel DMA; each channel operates

independently of the other. Within the operation of the individual channels, several different data

transfer modes are available. These modes can be combined in various configurations to provide a

very versatile DMA controller. Its feature set has enhancements beyond the 8237 DMA family;

however, it can be configured such that it can be used in an 8237-like mode. Each channel can

transfer data between any combination of memory and I/O with any combination (8 or 16 bits) of

data path widths. An internal temporary register that can disassemble or assemble data to or from

either an aligned or a nonaligned destination or source optimizes bus bandwidth.

The bus arbiter, a part of the DMA controller, works much like the priority resolving circuitry of a

DMA. It receives service requests from the two DMA channels, the external bus master, and the

DRAM Refresh Control Unit. The bus arbiter requests bus ownership from the core and resolves

priority issues among all active requests when bus mastership is granted.

Each DMA channel consists of three major components: the Requestor, the Target, and the Byte

Count. These components are identified by the contents of programmable registers that define the

memory or I/O device being serviced by the DMA. The Requestor is the device that requires and

requests service from the DMA controller. Only the Requestor is considered capable of initializing

80386EX Datasheet(PDF) 21 Page - Intel Corporation

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