80386EX datasheet(39/56 Pages) INTEL

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Intel386™ EX Embedded Microprocessor

Datasheet

t42a

UCS#, CS6:0# Hold after

WR# High

t42b

A25:1. BHE#, BLE# Hold

After WR# High

(7, 8)

t43

D15:0 Output Valid to WR#

High

2CLK2

– 10

2CLK2

– 10

(5)

t44

D15:0 Output Hold After WR#

High

CLK2

–10

CLK2

–10

t45

WR# High to D15:0 Float

CLK2

+ 10

CLK2

+10

(3)

t46

WR# Pulse Width

2CLK2

–10

2CLK2

–10

(7)

t47

A25:1, BHE#, BLE# Valid to

D15:0 Valid

4CLK2-

4CLK2

- 45

(5)

t47a

UCS#, CS6:0# Valid to D15-

D0 Valid

4CLK2 -

4CLK2

- 53

(5)

t48

RD# Low to D15:0 Input Valid

3CLK2 –

3CLK2

– 43

(5)

t49

D15:0 Hold After RD# High

t50

RD# High to D15:0 Float

CLK2

(3)

t51

A25:1, BHE#, BLE# Hold

After RD# High

t51a

UCS#, CS6:0# Hold after

RD# High

t52

RD# Pulse Width

3CLK2

–13

3CLK2

–15

Synchronous Serial I/O (SSIO) Unit

t100

STXCLK, SRXCLK

Frequency (Master Mode)

CLK2/8

(Unit is MHz)

t101

STXCLK, SRXCLK

Frequency (Slave Mode)

CLK2/8

(Unit is MHz)

t102

STXCLK, SRXCLK Low Time

7CLK2/

(2)

Table 12. 3-Volt AC Characteristics (Sheet 3 of 5)

Symbol

Parameter

25 MHz

3.0 V to 3.6 V

20 MHz

2.7 V to 3.6 V

Test Condition

Min.

(ns)

Max.

(ns)

Min.

(ns)

Max.

(ns)

NOTE:

1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating

frequencies.

2. These are not tested. They are guaranteed by characterization.

3. Float condition occurs when maximum output current becomes less than I

LO in magnitude. Float delay is not

fully tested.

4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure

recognition within a specific CLK2 period.

5. These specifications are for information only and are not tested. They are intended to assist the designer in

selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.

6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes

inactive as a result of READY# falling.

7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes

inactive as a result of phase 2 rising.

8. This specification applies if READY# is generated internally.

80386EX Datasheet(PDF) 39 Page - Intel Corporation

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