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80386EX Datasheet(PDF) 53 Page - Intel Corporation |
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80386EX Datasheet(HTML) 53 Page - Intel Corporation |
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53 / 56 page ![]() Intel386™ EX Embedded Microprocessor Datasheet 53 Figure 26. Halt Cycle A2492-02 LOCK# D15:0 CLK2 BHE#, A1, M/IO#, W/R# RD# READY# T1 T2 T1 T2 Ti Ti Ti Ti Cycle 1 Nonpipelined (Write) [Late Ready] CLKOUT Cycle 2 Nonpipelined (Halt) ADS# NA# A25:2, BLE#, D/C# WR# LBA# Idle Float Valid 1 CPU remains halted until INTR, SMI#, NMI, or RESET is asserted. CPU responds to HOLD input while in the HALT state. HALT cycle must be acknowledged by READY# asserted. This READY# could be generated internally or externally. Valid 2 † † Out Undefined Valid 1 Valid 1 |
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