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80386EX Datasheet(PDF) 33 Page - Intel Corporation

Part # 80386EX
Description  Intel386 EX Embedded Microprocessor
PDF  56 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

80386EX Datasheet(HTML) 33 Page - Intel Corporation

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Intel386™ EX Embedded Microprocessor
Datasheet
33
t20
READY#, BS8# Hold Time
4
4
t21
D15:0 Read Setup Time
7
7
t22
D15:0 Read Hold Time
4
4
t23
HOLD Setup Time
8
8
t24
HOLD Hold Time
3
3
t25
RESET Setup Time
5
5
t26
RESET Hold Time
2
3
t27
NMI Setup Time
6
6
(4)
t27a
SMI# Setup Time
6
6
(4)
t28
NMI Hold Time
6
6
(4)
t28a
SMI# Hold Time
6
6
(4)
t29
PEREQ, ERROR#, BUSY# Setup
Time
6
6
(4)
t30
PEREQ, ERROR#, BUSY# Hold
Time
5
5
(4)
t31
READY# Valid Delay
4
24
4
26
CL = 30 pF
t32
READY# Float Delay
4
34
4
34
t33
LBA# Valid Delay
4
20
4
22
t34
CS6:0#, UCS# Valid Delay
4
24 (25 in
SMM)
430
CL = 30 pF
t35
CLKOUT Valid Delay
2
9
2
14
CL = 30 pF
t36
PWRDOWN Valid Delay
4
15
4
18
t41
A25:1, BHE#, BLE# Valid to WR#
Low
00
t41a
UCS#, CS6:0# Valid to WR# Low
0
0
t42
A25:1, BHE#, BLE# Hold After
WR# High
0
0
(6)
t42a
UCS#, CS6:0# Hold after WR#
High
00
t42b
A25:1. BHE#, BLE# Hold After
WR# High
10
10
(7, 8)
Table 11. 5-Volt AC Characteristics (Sheet 2 of 5)
Symbol
Parameter
33 MHz
25 MHz
Test Condition
Min.
(ns)
Max.
(ns)
Min.
(ns)
Max.
(ns)
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than I
LO in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure recognition
within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.



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