80386EX datasheet(18/56 Pages) INTEL

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Intel386™ EX Embedded Microprocessor

Datasheet

TRST#

TAP (Test Access Port) Controller Reset resets the TAP

controller at power-up and each time it is activated. It has a

permanent weak pull-up resistor.

TXD1

H(Q)

R(1)

I(Q)

P(X)/P(Q)

Note 1

Transmit Data SIO1 and SIO0 transmit serial data from the

individual serial channels. TXD1 is multiplexed with DACK1#,

and TXD0 is multiplexed with P2.6.

TXD0

H(Q)

R(WL)

I(Q)

P(X)/P(Q)

Note 1

Transmit Data SIO1 and SIO0 transmit serial data from the

individual serial channels. TXD1 is multiplexed with DACK1#,

and TXD0 is multiplexed with P2.6.

UCS#

H(1)

R(0)

I(Q)

P(X)

Upper Chip-select is activated when the address of a memory

or I/O bus cycle is within the address region programmed by the

user.

System Power provides the nominal DC supply input. This pin is

connected externally to a V

CC board plane.

System Ground provides the 0 V connection from which all

inputs and outputs are measured. This pin is connected

externally to a ground board plane.

WDTOUT

H(Q)

R(0)

I(Q)

P(X)

Watchdog Timer Output indicates that the watchdog timer has

expired.

W/R#

H(Z)

R(0)

I(1)

P(1)

Write/Read indicates whether the current bus cycle is a write

cycle or a read cycle. When W/R# is HIGH, the bus cycle is a

write cycle; when W/R# is LOW, the bus cycle is a read cycle.

WR#

H(1)

R(1)

I(1)

P(1)

Write Enable indicates that the current bus cycle is a write cycle.

Table 4.

Intel386™ EX Microprocessor Pin Descriptions (Sheet 6 of 6)

Symbol

Type

Output States

Name and Function

NOTES:

1. X if clock source is internal; Q if clock source is external

2. Q if JTAG unit is shifting out data, Z if it is not

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