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80386EX Datasheet(PDF) 32 Page - Intel Corporation |
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80386EX Datasheet(HTML) 32 Page - Intel Corporation |
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32 / 56 page ![]() Intel386™ EX Embedded Microprocessor 32 Datasheet Table 11. 5-Volt AC Characteristics (Sheet 1 of 5) Symbol Parameter 33 MHz 25 MHz Test Condition Min. (ns) Max. (ns) Min. (ns) Max. (ns) Operating Frequency 0 33 0 25 one-half CLK2 frequency in MHz (1) t1 CLK2 Period 15 20 t2a CLK2 High Time 6.25 7 (2) t2b CLK2 High Time 4 4 (2) t3a CLK2 Low Time 6.25 7 (2) t3b CLK2 Low Time 4.5 5 (2) t4 CLK2 Fall Time 4 7 (2) t5 CLK2 Rise Time 4 7 (2) t6 A25:1 Valid Delay 4 21 4 24 C L = 50 pF t7 A25:1 Float Delay 4 28 4 28 (3) t8 BHE#, BLE#, LOCK# Valid Delay 4 21 4 24 C L = 50 pF t8a SMIACT# Valid Delay 4 21 4 24 CL = 50 pF t9 BHE#, BLE#, LOCK# Float Delay 4 28 4 28 (3) t10 M/IO#, D/C#, W/R#, ADS#, REFRESH# Valid Delay 421 4 24 CL = 50 pF t10a RD#, WR# Valid Delay 4 18 4 22 t10b WR# Valid Delay for the rising edge with respect to phase two (external late READY#) 4 28 4 28 (6) t11 M/IO#, D/C#, W/R#, REFRESH#, ADS# Float Delay 4 28 4 28 (3) t12 D15:0 Write Data Valid Delay 4 23 4 23 CL = 50 pF t13 D15:0 Write Data Float delay 4 22 4 22 (3) t14 HLDA Valid Delay 4 18 4 22 CL = 50 pF t15 NA# Setup Time 5 5 t16 NA# Hold Time 3 3 t19 READY# Setup Time 8 9 t19a BS8# Setup Time 11 11 NOTE: 1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. These are not tested. They are guaranteed by characterization. 3. Float condition occurs when maximum output current becomes less than I LO in magnitude. Float delay is not fully tested. 4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure recognition within a specific CLK2 period. 5. These specifications are for information only and are not tested. They are intended to assist the designer in selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification. 6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes inactive as a result of READY# falling. 7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes inactive as a result of phase 2 rising. 8. This specification applies if READY# is generated internally. |
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