LTC2992 datasheet(20/46 Pages) LINER

20 / 46 page

LTC2992

Rev A

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APPLICATIONS INFORMATION

the read byte command is available to the 0xE7 and 0xE8

(MFR_SPECIAL_ID) registers (Table 4).

I2C Device Addressing

Nine distinct I2C bus addresses are configurable using

the three-state pins ADR0 and ADR1, as shown in Table

3. ADR0 and ADR1 should be tied to INTVCC, to GND, or

left floating (NC) to configure the lower four address bits.

During low power shutdown, the address select state

is latched into memory powered from standby supply.

Address bits a6, a5 and a4 are permanently set to 110

and the least significant bit is the R/W bit. In addition, all

LTC2992 devices will respond to a common mass write

address (1100110)b; this allows the bus master to write

to several LTC2992s simultaneously, regardless of their

individualaddresssettings.TheLTC2992willalsorespond

to the standard SMBus ARA address (0001100)b if the

GPIO4 (ALERT) pin is asserted. See the Alert Response

Protocol section for more details. The LTC2992 will not

respond to the ARA address if no alerts are pending.

Start and Stop Conditions

When the I2C bus is idle, both SCL and SDA are in the high

state. A bus master signals the beginning of a transmis-

sion with a START condition by transitioning SDA from

high to low while SCL stays high. When the master has

finished communicating with the slave, it issues a STOP

Figure 8. General Data Transfer Over I2C

Figure 9. Serial Bus SDA Write Byte Protocol

Figure 10. Serial Bus SDA Write Word Protocol

Figure 11. Serial Bus SDA Write Page Protocol

Figure 12. Serial Bus SDA Read Byte Protocol

Figure 14. Serial Bus SDA Read Page Protocol

Figure 13. Serial Bus SDA Read Word Protocol

SDA

SCL

a6 - a0

b7 - b0

1 - 7

START

CONDITION

STOP

CONDITION

ADDRESS

ACK

DATA

ACK

R/W

2992 F08

S ADDRESS

1 1 0 a3:a0

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

A: ACKNOWLEDGE (LOW)

A: NOT ACKNOWLEDGE (HIGH)

R: READ BIT (HIGH)

COMMAND

DATA

b7:b0

A P

2992 F09

W: WRITE BIT (LOW)

S: START CONDITION

P: STOP CONDITION

S ADDRESS

1 1 0 a3:a0

COMMAND

DATA

b7:b0

2992 F10

b7:b0

A P

S ADDRESS

1 1 0 a3:a0

COMMAND

b7:b0

2992 F11

A P

b7:b0

DATA

b7:b0

DATA

...

b7:b0

DATA

S ADDRESS

1 1 0 a3:a0

1 1 0 a3:a0 1 0

COMMAND

S ADDRESS R A

b7:b0 1

DATA

b7:b0

2992 F12

A P

S ADDRESS

1 1 0 a3:a0

1 1 0 a3:a0 1 0

COMMAND

S ADDRESS R A

b7:b0

DATA

b7:b0

2992 F13

b7:b0

DATA

A P

S ADDRESS

1 1 0 a3:a0

1 1 0 a3:a0 1 0

COMMAND

S ADDRESS R A

b7:b0

DATA

b7:b0

2992 F14

b7:b0

DATA

A P

...

b7:b0

DATA

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