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LTC3111

3111fa

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APPLICATIONS INFORMATION

However, with higher losses in the power stage (larger

RS) the Q factor will be lower and the phase loss will occur

more gradually. As a result, the power stage phase will

not be as close to –180° at the crossover frequency and

less phase boost is required of the compensation network.

The LTC3111 error amplifier is designed to have a fixed

maximum bandwidth in order to provide rejection of

switching noise to prevent it from interfering with the

control loop. From a frequency domain perspective, this

can be viewed as an additional single pole as illustrated

in Figure 9. The nominal frequency of this pole is 400kHz.

For typical loop crossover frequencies below about 60kHz

the phase contributed by this additional pole is negligible.

However, for loops with higher crossover frequencies this

additional phase loss should be taken into account when

designing the compensation network.

the worst-case inductor current ripple to less than 1A peak

to peak. A low ESR output capacitor with a value of 22µF

is specified to yield a worst-case output voltage ripple

(occurring at the worst-case step-up ratio and maximum

load current) of approximately 20mV. In summary, the

key power stage specifications for this LTC3111 example

application are given below.

f = 0.8MHz, tLOW = 160ns

VIN = 3.5V to 15V

VOUT = 5V at R = 10Ω

COUT = 22µF, RC = 10mΩ

L = 4.7µH, RL = 25mΩ

RS = 200mΩ

With the power stage parameters specified, the compen-

sation network can be designed. In most applications,

the most challenging compensation corner is boost

mode operation at the greatest step-up ratio and highest

load current since this generates the lowest frequency

right-half-plane zero and results in the greatest phase

loss. Therefore, a reasonable approach is to design the

compensation network at this worst-case corner and then

verify that sufficient phase margin exists across all other

operating conditions. In this example application, at VIN =

3.5V and the full 500mA load current, the right-half-plane

zero will be located at 136kHz and this will be a dominant

factor in determining the bandwidth of the control loop.

The first step in designing the compensation network is

to determine the target crossover frequency for the com-

pensated loop. A reasonable starting point is to assume

that the compensation network will generate a peak phase

boost of approximately 60°. Therefore, in order to obtain

a phase margin of 60°, the loop crossover frequency, fC,

should be selected as the frequency at which the phase

0.8V

RFILT

CFILT

3111 F09

LTC3111

COMP

–

Figure 9. Internal Loop Filter

Loop Compensation Example

This section provides an example illustrating the design of

a compensation network for a typical LTC3111 application

circuit. In this example a 5V regulated output voltage is

generated with the ability to supply a 500mA load from an

input power source ranging from 3.5V to 15V. To reduce

switching losses a 800kHz switching frequency has been

chosen for this example. In this application the maximum

inductor current ripple will occur at the highest input volt-

age. An inductor value of 4.7µH has been chosen to limit

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