LTM4645 datasheet(25/34 Pages) LINER

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LTM4645

4645f

For more information www.linear.com/LTM4645

applicaTions inForMaTion

ambient temperature change is factored into the derating

curves. The junctions are maintained at ~120°C maximum

while lowering output current or power with increasing

ambient temperature. The decreased output current will

decrease the internal module loss as ambient temperature

isincreased.Themonitoredjunctiontemperatureof120°C

minus the ambient operating temperature specifies how

much module temperature rise can be allowed, as an ex-

ample, in Figure 20 the load current is derated to 15A at

100°C with no air or heat sink and the power loss for the

12V to 1.5V at 15A output is about 3.5W. The 3.5W loss

is calculated with the 2.7W room temperature loss from

the 12V to 1.5V power loss curve at 15A, from Figure 13,

and the 1.3 multiplying factor at 120°C junction. If the

100°C ambient temperature is subtracted from the 120°C

junction temperature, then the difference of 20°C divided

by 3.5W equals a 5.7°C/W

θJA thermal resistance. Table

4 specifies a 5.5°C/W value which is very close. Tables 3

and 4 provide equivalent thermal resistances for 1.0V and

1.5Voutputswithandwithoutairflowandheatsinking.The

derivedthermalresistancesinTables3and4forthevarious

conditions can be multiplied by the calculated power loss

asafunctionofambienttemperaturetoderivetemperature

rise above ambient, thus maximum junction temperature.

Room temperature power loss can be derived from the ef-

ficiency curves in the Typical Performance Characteristics

section and adjusted with the above ambient temperature

multiplicative factors. The printed circuit board is a 1.6mm

thick six layer board with two ounce copper for all layers.

The PCB dimensions are 95mm

× 76mm. The BGA heat

sinks are listed in Table 4.

Layout Checklist/Example

The high integration of LTM4645 makes the PCB board

layout very simple and easy. However, to optimize its

electrical and thermal performance, some layout consid-

erations are still necessary.

• Use large PCB copper areas for high current paths,

including VIN, GND, and VOUT. It helps to minimize the

PCB conduction loss and thermal stress.

• Place high frequency ceramic input and output capaci-

tors next to the VIN, PGND and VOUT pins to minimize

high frequency noise.

• Place a dedicated power ground layer underneath the

unit.

• To minimize the via conduction loss and reduce module

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

• Do not put via directly on the pad, unless they are

capped or plated over.

• Use a separated SGND ground copper area for com-

ponents connected to signal pins. Connect the SGND

to GND underneath the unit.

• For parallel modules, tie the VOUT, VFB, and COMP pins

together. Use an internal layer to closely connect these

pins together. The TRACK pin can be tied a common

capacitor for regulator soft-start.

• Bring out test points on the signal pins for monitoring.

Figure22givesagoodexampleoftherecommendedlayout.

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