ISL6527IBZ datasheet(10/17 Pages) RENESAS

10 / 17 page

ISL6527, ISL6527A

FN9056 Rev 11.00

Page 10 of 17

Sep 29, 2015

The modulator transfer function is the small-signal transfer

function of VOUT/VE/A. This function is dominated by a DC

Gain and the output filter (LO and CO), with a double pole

break frequency at FLC and a zero at FESR. The DC Gain of

the modulator is simply the input voltage (VIN) divided by the

peak-to-peak oscillator voltage

VOSC.

Modulator Break Frequency Equations

The compensation network consists of the error amplifier

(internal to the ISL6527, ISL6527A) and the impedance

networks ZIN and ZFB. The goal of the compensation

network is to provide a closed loop transfer function with the

highest 0dB crossing frequency (f0dB) and adequate phase

margin. Phase margin is the difference between the closed

loop phase at f0dB and 180°. Equations 7 through 10 relate

the compensation network’s poles, zeros and gain to the

components (R1, R2, R3, C1, C2, and C3) in Figure 5. Use

these guidelines for locating the poles and zeros of the

compensation network:

1. Pick gain (R2/R1) for desired converter bandwidth.

2. Place first zero below filter’s double pole (~75% FLC).

3. Place second zero at filter’s double-pole.

4. Place first pole at the ESR zero.

5. Place second pole at half the switching frequency.

6. Check gain against error amplifier’s open-loop gain.

7. Estimate phase margin; repeat if necessary.

Compensation Break Frequency Equations

Figure 6 shows an asymptotic plot of the DC/DC converter’s

gain vs frequency. The actual modulator gain has a high gain

peak due to the high Q factor of the output filter and is not

shown in Figure 6. Using the above guidelines should give a

compensation gain similar to the curve plotted. The open loop

VOUT

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

LOUT

COUT

CIN

+3.3V VIN

KEY

COMP

ISL6527, ISL6527A

UGATE

CBP

GND

CPVOUT

FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES

AND ISLANDS

BOOT

VIA CONNECTION TO GROUND PLANE

CBOOT

PHASE

LGATE

PHASE

VCC

CVCC

FLC

 x L

O x CO

------------------------------------------

(EQ. 5)

FESR

 x ESR x C

-------------------------------------------

(EQ. 6)

FIGURE 5. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

VOUT

REFERENCE

ESR

VIN

DVOSC

ERROR

AMP

PWM

DRIVER

(PARASITIC)

ZFB

REFERENCE

COMP

VOUT

ZFB

ISL6527

ZIN

COMPARATOR

DRIVER

DETAILED COMPENSATION COMPONENTS

PHASE

VE/A

ZIN

OSC

FZ1

 R



----------------------------------

(EQ. 7)

FP1

 x R

2 x

C1 x C2

C1 C2

----------------------







---------------------------------------------------------

(EQ. 8)

FZ2

 x R

 x C

-------------------------------------------------------

(EQ. 9)

FP2

 x R

3 x C3

------------------------------------

(EQ. 10)

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