ISL6527, ISL6527A

FN9056 Rev 11.00

Page 11 of 17

Sep 29, 2015

error amplifier gain bounds the compensation gain. Check the

amplifier. The closed loop gain is constructed on the graph of

Figure 6 by adding the modulator gain (in dB) to the

compensation gain (in dB). This is equivalent to multiplying

the modulator transfer function to the compensation transfer

function and plotting the gain.

The compensation gain uses external impedance networks

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45°.

Include worst-case component variations when determining

phase margin.

Component Selection Guidelines

Charge Pump Capacitor Selection

A capacitor across pins CT1 and CT2 is required to create the

proper bias voltage for the ISL6527, ISL6527A when operating

the IC from 3.3V. Selecting the proper capacitance value is

important so that the bias current draw and the current required

by the MOSFET gates do not overburden the capacitor. A

conservative approach is presented in Equation 11:

Output Capacitor Selection

An output capacitor is required to filter the output and supply

the load transient current. The filtering requirements are a

function of the switching frequency and the ripple current.

The load transient requirements are a function of the slew

rate (di/dt) and the magnitude of the transient load current.

These requirements are generally met with a mix of

capacitors and careful layout.

Modern digital ICs can produce high transient load slew

rates. High frequency capacitors initially supply the transient

and slow the current load rate seen by the bulk capacitors.

The bulk filter capacitor values are generally determined by

the ESR (Effective Series Resistance) and voltage rating

requirements rather than actual capacitance requirements.

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements.

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors. The

bulk capacitor’s ESR will determine the output ripple voltage

and the initial voltage drop after a high slew-rate transient. An

aluminum electrolytic capacitor’s ESR value is related to the

case size with lower ESR available in larger case sizes.

However, the Equivalent Series Inductance (ESL) of these

capacitors increases with case size and can reduce the

usefulness of the capacitor to high slew-rate transient loading.

Unfortunately, ESL is not a specified parameter. Work with

your capacitor supplier and measure the capacitor’s

impedance with frequency to select a suitable component. In

most cases, multiple electrolytic capacitors of small case size

perform better than a single large case capacitor.

Output Inductor Selection

The output inductor is selected to meet the output voltage

ripple requirements and minimize the converter’s response

time to the load transient. The inductor value determines the

converter’s ripple current and the ripple voltage is a function

of the ripple current. The ripple voltage and current are

approximated by Equations 12 and 13:

Increasing the value of inductance reduces the ripple current

and voltage. However, the large inductance values reduce

the converter’s response time to a load transient.

One of the parameters limiting the converter’s response to

a load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

ISL6527, ISL6527A will provide either 0% or 100% duty

cycle in response to a load transient. The response time is

the time required to slew the inductor current from an initial

current value to the transient current level. During this

interval the difference between the inductor current and the

transient current level must be supplied by the output

capacitor. Minimizing the response time can minimize the

output capacitance required.

The response time to a transient is different for the application

of load and the removal of load. Equations 14 and 15 give the

FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

100

80

60

40

20

0

-20

-40

-60

FP1

FZ2

10M

1M

100k

10k

1k

100

10

OPEN LOOP

ERROR AMP GAIN

FZ1

FP2

FLC

FESR

COMPENSATION

FREQUENCY (Hz)

GAIN

MODULATOR

GAIN

LOOP GAIN

20

VIN

VOSC

------------------







log

20

R2

R1

--------





log



------------------------------------ 1.5



=

(EQ. 11)

I=

x

(EQ. 12)

(EQ. 13)