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FNP3000 Datasheet(PDF) 7 Page - Bel Fuse Inc. |
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FNP3000 Datasheet(HTML) 7 Page - Bel Fuse Inc. |
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7 / 17 page ![]() FNP3000 Series 7 Asia-Pacific +86 755 298 85888 Europe, Middle East +353 61 225 977 North America +1 408 785 5200 © 2018 Bel Power Solutions & Protection BCD.00669_004 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 0 1 1 A2 A1 A0 R/W The following features will be offered as “standard” by the base product: This feature shall provide write-protected Vital Product Data (VPD) which shall include the following: • Revision level • CUI Date Code and origin of manufacture • CUI Serial number (from the product label) is the last 5 or 6 maximum numbers, and is padded with zeros to fit the PMBus® variable as 8 bytes total The product’s 7-bit I2C slave address is formed by determining the logic state of the address pins A0, A1 and A2. A pull-up resistor shall be supplied within the product for each address pin. The values of A0, A1 and A2 are set in the backplane of the system. Thus the device can be set to respond to all 7-bit addresses in the range from binary 1011 000 to 1011 111. The address pins shall be read once the micro-controllers have been initialized. To prevent hot swapping from latching the slave address to a specific slot in the enclosure, the software shall continuously read and update at an interval of 1 s the slave address accordingly. The product is provided with a digital communications interface that is based upon a subset of the SMBus™ & PMBus® Protocols. The communication interface is a Two Wire Interface (TWI) using devices hardware compatible with I2C. The interface is based upon the I2C Protocol developed by Philips Semiconductors (now NXP). Reference to the “I2C Bus Specification and User Manual” UM10204 Rev.03 – 19 June 2007 is recommended. Refer to the PMBus®/SMBus specification for details on read/write operations when dealing with Byte, Word or Block process calls. Packet Error Correction (PEC) and Address Resolution Protocol (ARP) are not supported. If the PMBus® master tries to read more bytes than the length of the data selected by the command code, the additional bytes will be sent as 0xFF. The PMBus® slave device may apply clock stretching by holding the clock line (SCL) low after a command to indicate that it is busy processing data. A master device on the PMBus® bus may attempt to continue with the communications but must first wait until the clock line is released. Clock stretching times will vary depending on the data being processed and/ or if there are any higher priority events occur during the response but shall not exceed 25 ms. |
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