ISL6565BCB datasheet(13/28 Pages) RENESAS

13 / 28 page

ISL6565A, ISL6565B

FN9135 Rev 4.00

Page 13 of 28

Dec 1, 2005

The filtered error signal modifies the pulse width

commanded by VCOMP to correct any unbalance and force

IER toward zero. The same method for error signal

correction is applied to each active channel.

Channel-current balance is essential in realizing the thermal

advantage of multi-phase operation. The heat generated in

conversion is dissipated over multiple devices and a large

area. The designer avoids the complexity of driving multiple

parallel MOSFETs, and the expense of using heat sinks and

non-standard magnetic materials.

Voltage Regulation

The integrating compensation network shown in Figure 7

insures that the steady-state error in the output voltage is

limited only to the error in the reference voltage (output of

the DAC) and offset errors in the OFS current source,

remote-sense and error amplifiers. Intersil specifies the

guaranteed tolerance of the ISL6565A, ISL6565B to include

the combined tolerances of each of these elements.

The output of the error amplifier, VCOMP, is compared to the

sawtooth waveform to generate the PWM signals. The PWM

signals control the timing of the Intersil MOSFET drivers and

regulate the converter output to the specified reference

voltage. The internal and external circuitry that controls

voltage regulation is illustrated in Figure 7.

The ISL6565 incorporates an internal differential remote-

sense amplifier in the feedback path. The amplifier removes

the voltage error encountered when measuring the output

voltage relative to the controller ground reference point

resulting in a more accurate means of sensing output

voltage. Connect the microprocessor sense pins to the non-

inverting input, VSEN, and inverting input, RGND, of the

remote-sense amplifier. The remote-sense output, VDIFF, is

connected to the inverting input of the error amplifier through

an external resistor.

A digital to analog converter (DAC) generates a reference

voltage based on the state of logic signals at pins VID4

through VID12.5. The DAC decodes the 6-bit logic signal

(VID) into one of the discrete voltages shown in Table 1.

Each VID input offers a 20

A pull-up to an internal 2.5V

source for use with open-drain outputs. The pull-up current

diminishes to zero above the logic threshold to protect

voltage-sensitive output devices. External pull-up resistors

can augment the pull-up current sources in case leakage

into the driving device is greater than 20

A.

FIGURE 6. CHANNEL-1 PWM FUNCTION AND CURRENT-

BALANCE ADJUSTMENT

N

IAVG

I3 *



f(s)

PWM1

VCOMP

SAWTOOTH SIGNAL

IER

NOTE: *CHANNEL 3 IS OPTIONAL.

FILTER

FIGURE 7. OUTPUT VOLTAGE AND LOAD-LINE

REGULATION WITH OFFSET ADUJUSTMENT

IAVG

EXTERNAL CIRCUIT

ISL6565 INTERNAL CIRCUIT

COMP

RFB

VDIFF

VSEN

RGND

VDROOP

ERROR AMPLIFIER

VOUT+

DIFFERENTIAL

REMOTE-SENSE

AMPLIFIER

VCOMP

REF

RTCOMP

CREF

VOUT-

VID DAC

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