ISL6565BCB datasheet(24/28 Pages) RENESAS

24 / 28 page

ISL6565A, ISL6565B

FN9135 Rev 4.00

Page 24 of 28

Dec 1, 2005

have sufficiently low ESL and ESR so that the total output-

voltage deviation is less than the allowable maximum.

Neglecting the contribution of inductor current and regulator

response, the output voltage initially deviates by an amount

The filter capacitor must have sufficiently low ESL and ESR

so that

V < VMAX.

Most capacitor solutions rely on a mixture of high-frequency

capacitors with relatively low capacitance in combination

with bulk capacitors having high capacitance but limited

high-frequency performance. Minimizing the ESL of the

high-frequency capacitors allows them to support the output

voltage as the current increases. Minimizing the ESR of the

bulk capacitors allows them to supply the increased current

with less output voltage deviation.

The ESR of the bulk capacitors also creates the majority of

the output-voltage ripple. As the bulk capacitors sink and

source the inductor AC ripple current (see Interleaving and

Equation 2), a voltage develops across the bulk-capacitor

ESR equal to IC,PP(ESR). Thus, once the output capacitors

are selected, the maximum allowable ripple voltage,

VPP(MAX), determines the lower limit on the inductance.

Since the capacitors are supplying a decreasing portion of

the load current while the regulator recovers from the

transient, the capacitor voltage becomes slightly depleted.

The output inductors must be capable of assuming the entire

load current before the output voltage decreases more than

VMAX. This places an upper limit on inductance.

Equation 43 gives the upper limit on L for the cases when

the trailing edge of the current transient causes a greater

output-voltage deviation than the leading edge. Equation 44

addresses the leading edge. Normally, the trailing edge

dictates the selection of L because duty cycles are usually

less than 50%. Nevertheless, both inequalities should be

evaluated, and L should be selected based on the lower of

the two results. In each equation, L is the per-channel

inductance, C is the total output capacitance, and N is the

number of active channels.

Input Supply Voltage Selection

The VCC input of the ISL6565 can be connected either

directly to a +5V supply or through a current limiting resistor to

a +12V supply. An integrated 5.8V shunt regulator maintains

the voltage on the VCC pin when a +12V supply is used. A

300

 resistor is suggested for limiting the current into the

VCC pin to a worst-case maximum of approximately 25mA.

Switching Frequency

There are a number of variables to consider when choosing

the switching frequency, as there are considerable effects on

the upper-MOSFET loss calculation. These effects are

outlined in MOSFETs, and they establish the upper limit for

the switching frequency. The lower limit is established by the

requirement for fast transient response and small output-

voltage ripple as outlined in Output Filter Design. Choose the

lowest switching frequency that allows the regulator to meet

the transient-response requirements.

Switching frequency is determined by the selection of the

frequency-setting resistor, RT (see the figures labeled

Typical Application

on pages 5 and 6). Figure 18 and

Equation 45 are provided to assist in selecting the correct

value for RT.

Input Capacitor Selection

The input capacitors are responsible for sourcing the AC

component of the input current flowing into the upper

MOSFETs. Their RMS current capacity must be sufficient to

handle the AC component of the current drawn by the upper

MOSFETs which is related to duty cycle and the number of

active phases.

V

ESL

 di

-----

ESR

 I



(EQ. 41)

ESR



VIN NVOUT

–



 V

OUT

fSVINVPP MAX



------------------------------------------------------------



(EQ. 42)

2NCVO

I

2

---------------------

V

MAX

I ESR



–



(EQ. 43)

1.25

NC

I

2

--------------------------

V

MAX

I ESR



–

VIN VO

–







(EQ. 44)

10.7 1.045



log

–



(EQ. 45)

FIGURE 18. RT vs SWITCHING FREQUENCY

SWITCHING FREQUENCY (kHz)

1000

100

1000

10000

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