DLPC3479 datasheet(32/61 Pages) TI1

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DLPC3479

DLPS112 – JUNE 2018

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Feature Description (continued)

NOTE

VSYNC_WE must remain active at all times (in lock-to-VSYNC mode) or the display

sequencer will stop and cause the LEDs to be turned off.

8.3.2 Serial Flash Interface

The DLPC3479 uses an external SPI serial flash memory device for configuration support. The minimum

required size is dependent on the desired minimum number of sequences, CMT tables, and splash options while

the maximum supported size is 64 Mb.

For access to flash, the DLPC3479 uses a single SPI interface operating at a programmable frequency

complying to industry standard SPI flash protocol. The programmable SPI frequency is defined to be equal to

180 MHz/N, where N is a programmable value between 5 to 127 providing a range from 36.0 to 1.41732 MHz.

Note that this results in a relatively large frequency step size in the upper range (for example, 36 MHz, 30 MHz,

25.7 MHz, 22.5 MHz, and so forth) and thus this must be taken into account when choosing a flash device.

The DLPC3479 supports two independent SPI chip selects; however, the flash must be connected to SPI chip

select zero (SPI0_CSZ0) because the boot routine is only executed from the device connected to chip select

zero (SPI0_CSZ0). The boot routine uploads program code from flash to program memory, then transfers control

to an auto-initialization routine within program memory. The DLPC3479 asserts the HOST_IRQ output signal

high while auto-initialization is in progress, then drives it low to signal its completion to the host processor. Only

after auto-initialization is complete will the DLPC3479 be ready to receive commands through I2C.

The DLPC3479 supports flash devices that are compatible with the modes of operation, features, and

performance as defined in Table 3 and Table 4.

Table 3. SPI Flash Required Features or Modes of Operation

Feature

DLPC3479 Requirement

SPI interface width

Single

SPI protocol

SPI mode 0

Fast READ addressing

Auto-incrementing

Programming mode

Page mode

Page size

256 B

Sector size

4 kB sector

Block size

Any size

Block protection bits

0 = Disabled

Status register bit(0)

Write in progress (WIP, also called flash busy)

Status register bit(1)

Write enable latch (WEN)

Status register bits(6:2)

A value of 0 disables programming protection

Status register bit(7)

Status register write protect (SRWP)

Status register bits(15:8)

(that is expansion status byte)

The DLPC3479 only supports single-byte status register R/W command execution, and thus may not be

compatible with flash devices that contain an expansion status byte. However, as long as the expansion

status byte is considered optional in the byte 3 position and any write protection control in this expansion

status byte defaults to unprotected, then the device is compatible with the DLPC3479.

To support flash devices with program protection defaults of either enabled or disabled, the DLPC3479 always

assumes the device default is enabled and goes through the process of disabling protection as part of the boot-

up process. This process consists of:

•

A write enable (WREN) instruction executed to request write enable, followed by

•

A read status register (RDSR) instruction is then executed (repeatedly as needed) to poll the write enable

latch (WEL) bit

•

After the write enable latch (WEL) bit is set, a write status register (WRSR) instruction is executed that writes

0 to all 8-bits (this disables all programming protection)

Prior to each program or erase instruction, the DLPC3479 issues:

•

A write enable (WREN) instruction to request write enable, followed by

DLPC3479 Datasheet(PDF) 32 Page - Texas Instruments

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