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DLPC3479 Datasheet(PDF) 39 Page - Texas Instruments |
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DLPC3479 Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 61 page  39 DLPC3479 www.ti.com DLPS112 – JUNE 2018 Product Folder Links: DLPC3479 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) Timing parameter C is always the sum of B+D. Table 7. 3D DLP Link Nominal Timing Table(1) HDMI SOURCE REFERENCE (Hz) 3D DMD SEQUENCE RATE (Hz) A (µs) B (µs) C (µs) D (µs) E (µs) 49.0 98 31.8 >500 >622 161.6 >2000 50.0 100 31.2 >500 >658 158.4 >2000 51.0 102 30.6 >500 >655 155.3 >2000 59.0 118 26.4 >500 >634 134.2 >2000 60.0 120 26.0 >500 >632 132.0 >2000 61.0 122 25.6 >500 >630 129.8 >2000 (1) Timing parameter C is always the sum of B+D. Table 8. 3D DLP Link Min/Max Timing Table(1) HDMI SOURCE REFERENCE (Hz) 3D DMD SEQUENCE RATE (Hz) A (µs) B (µs) C (µs) D (µs) E (µs) 49.0 98 20-32 >500 >628 128-163 >2000 50.0 100 20-32 >500 >628 128-163 >2000 51.0 102 20-32 >500 >628 128-163 >2000 59.0 118 20-32 >500 >628 128-163 >2000 60.0 120 20-32 >500 >628 128-163 >2000 61.0 122 20-32 >500 >628 128-163 >2000 8.3.10 DMD (Sub-LVDS) Interface The DLPC3479 ASIC DMD interface consists of a HS 1.8-V sub-LVDS output only interface with a maximum clock speed of 600-MHz DDR and a LS SDR (1.8-V LVCMOS) interface with a fixed clock speed of 120 MHz. Table 9 shows how the 8 sub-LVDS lanes are configured for the DLP4710 (.47 1080p) DMD. Table 9. DLP4710 (.47 1080p) DMD – ASIC to 8-Lane DMD Pin Mapping DLPC3479 ASIC 8 LANE DMD ROUTING OPTION #1 MASTER DLPC3479 PINS SLAVE DLPC3479 PINS DMD PINS HS_WDATA_D_P HS_WDATA_D_N HS_WDATA_E_P HS_WDATA_E_N Input DATA_p_0 Input DATA_n_0 HS_WDATA_C_P HS_WDATA_C_N HS_WDATA_F_P HS_WDATA_F_N Input DATA_p_1 Input DATA_n_1 HS_WDATA_B_P HS_WDATA_B_N HS_WDATA_G_P HS_WDATA_G_N Input DATA_p_2 Input DATA_n_2 HS_WDATA_A_P HS_WDATA_A_N HS_WDATA_H_P HS_WDATA_H_N Input DATA_p_3 Input DATA_n_3 HS_WDATA_H_P HS_WDATA_H_N HS_WDATA_A_P HS_WDATA_A_N Input DATA_p_4 Input DATA_n_4 HS_WDATA_G_P HS_WDATA_G_N HS_WDATA_B_P HS_WDATA_B_N Input DATA_p_5 Input DATA_n_5 HS_WDATA_F_P HS_WDATA_F_N HS_WDATA_C_P HS_WDATA_C_N Input DATA_p_6 Input DATA_n_6 HS_WDATA_E_P HS_WDATA_E_N HS_WDATA_D_P HS_WDATA_D_N Input DATA_p_7 Input DATA_n_7 DLPC3479 ASIC 8 LANE DMD ROUTING OPTION #2 MASTER DLPC3479 PINS SLAVE DLPC3479 PINS DMD PINS HS_WDATA_E_P HS_WDATA_E_N HS_WDATA_D_P HS_WDATA_D_N Input DATA_p_0 Input DATA_n_0 HS_WDATA_F_P HS_WDATA_F_N HS_WDATA_C_P HS_WDATA_C_N Input DATA_p_1 Input DATA_n_1 HS_WDATA_G_P HS_WDATA_G_N HS_WDATA_B_P HS_WDATA_B_N Input DATA_p_2 Input DATA_n_2 |
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