DLPC3479 datasheet(46/61 Pages) TI1

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PARKZ

PLL_REFCLK

RESETZ

I2C (activity)

HOST_IRQ

VDD_PLLM/D

(1.1 V)

VDD

(1.1 V)

VCC18

(1.8 V)

VDDLP12

(if not tied to VDD)

PROJ_ON input

(GPIO_8)

VCC_INTF

(1.8 to 3.3 V)

VCC_FLSH

(1.8 to 3.3 V)

0 µs (min)

500 ms (min)

(a)

5 ms (min)

0 µs (min)

0 µs (max)

(b)

0 µs (min)

(c)

32 µs (min)

(d)

(e)

DLPC3479

DLPS112 – JUNE 2018

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Product Folder Links: DLPC3479

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System Power-Up and Power-Down Sequence (continued)

t1: HOST_IRQ is driven high when power and RESETZ are applied to indicate the controller is not ready for

operation, and then is driven low after initialization is complete initialization is complete

t2: all supplies reach 95% of their specified nominal values.

t4: I2C access can start immediately after HOST_IRQ goes low (this should occur within 500 ms from the release of

RESETZ)

t6: I2C activity must cease immediately upon active low assertion of PARKZ T9 HOST_IRQ is pulled high immediately

after RESETZ is asserted low.

t8: All power supplies reach 95% of their specified nominal values.

t9: HOST_IRQ is pulled high immediately after RESETZ is asserted low.

(a) PLL_REFCLK may be active before power is applied.

(b) PARKZ must be set high a minimum of 0 µs before RESETZ is released to support auto-initialization.

specification.

(d) PARKZ must be set low a minimum of 32 µs before any power is removed (except VDDLP12), before

PLL_REFCLK is stopped and before RESETZ is asserted low to allow time for the DMD mirrors to be parked.

(e) PLL_REFCLK must become stable within 5 ms of all power being applied (for external oscillator application this is

oscillator dependent and for crystal applications this is crystal and ASIC oscillator cell dependent).

Figure 26. DLPC3479 Power-Up/PARKZ = 0 Initiated Fast PARK and Power-Down

DLPC3479 Datasheet(PDF) 46 Page - Texas Instruments

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