X9110

FN8158 Rev 5.00

Page 4 of 18

October 28, 2016

If the pause feature is not used, HOLD should be held HIGH at all

times.

DEVICE ADDRESS (A0)

The address input is used to set the 8-bit slave address. A match

in the slave address serial data stream A0 must be made with

the address input (A0) in order to initiate communication with

the X9110.

CHIP SELECT (CS)

When CS is HIGH, the X9110 is deselected and the SO pin is at

high impedance, and (unless an internal write cycle is underway)

the device will be in the standby state. CS LOW enables the

X9110, placing it in the active power mode. It should be noted

that after a power-up, a HIGH to LOW transition on CS is required

prior to the start of any operation.

HARDWARE WRITE PROTECT INPUT (WP)

The WP pin when LOW prevents nonvolatile writes to the Data

Registers.

Potentiometer Pins

a mechanical potentiometer.

The wiper pin are equivalent to the wiper terminal of a

mechanical potentiometer.

Bias Supply Pins

system ground.

ANALOG SUPPLY VOLTAGES (V+ AND V-)

These supplies are the analog voltage supplies for the

potentiometer. The V+ supply is tied to the wiper switches while

the V- supply is used to bias the switches and the internal P+

substrate of the integrated circuit. Both of these supplies set the

voltage limits of the potentiometer.

Principles of Operation

Device Description

SERIAL INTERFACE

The X9110 supports the SPI interface hardware conventions. The

device is accessed via the SI input with data clocked-in on the

rising SCK. CS must be LOW and the HOLD and WP pins must be

HIGH during the entire operation.

The SO and SI pins can be connected together, since they have

three state outputs. This can help to reduce system pin count.

ARRAY DESCRIPTION

The X9110 is comprised of a resistor array (Figure 3). The array

contains the equivalent of 1023 discrete resistive segments that

are connected in series. The physical ends of each array are

equivalent to the fixed terminals of a mechanical potentiometer

SERIAL DATA PATH

FROM INTERFACE

REGISTER 0

SERIAL

BUS

INPUT

PARALLEL

BUS

INPUT

COUNTER

REGISTER

R H

R L

R

W

10

10

C

O

U

N

T

E

R

D

E

C

O

D

E

WIPER

(WCR)

(DR0)

CIRCUITRY

REGISTER 1

(DR1)

REGISTER 2

(DR2)

REGISTER 3

(DR3)

FIGURE 3. DETAILED POTENTIOMETER BLOCK DIAGRAM

R