X9110

FN8158 Rev 5.00

Page 6 of 18

October 28, 2016

TABLE 5. INSTRUCTION BYTE FORMAT

Device Instructions

Identification Byte (ID and A)

The first byte sent to the X9110 from the host, following a CS

going HIGH to LOW, is called the Identification byte. The most

significant four bits of the slave address are a device type

identifier. The ID[3:0] bits is the device ID for the X9110; this is

fixed as 0101[B] (refer to Table 4).

The A0 bit in the ID byte is the internal slave address. The physical

device address is defined by the state of the A0 input pin. The slave

address is externally specified by the user. The X9110 compares

the serial data stream with the address input state; a successful

compare of the address bit is required for the X9110 to

successfully continue the command sequence. Only the device

whose slave address matches the incoming device address sent

by the master executes the instruction. The A0 input can be

R/W bit is used to set the device to either read or write mode.

Instruction Byte and Register Selection

The next byte sent to the X9110 contains the instruction and

register pointer information. The three most significant bits are

used provide the instruction opcode (I[2:0]). The RB and RA bits

point to one of the four registers. The format is shown in Table 5.

Five of the seven instructions are four bytes in length. These

instructions are:

1. Read Wiper Counter Register – This register reads the current

wiper position of the selected pot.

2. Write Wiper Counter Register – This register changes current

wiper position of the selected pot.

3. Read Data Register – This register reads the contents of the

selected data register.

4. Write Data Register – This register writes a new value to the

selected data register.

5. Read Status – This command returns the contents of the WIP

bit, which indicates if the internal write cycle is in progress.

The basic sequence of the four byte instructions is illustrated in

Figure 5 on page 7. These four-byte instructions exchange data

between the WCR and one of the Data Registers. A transfer from

a Data Register to a WCR is essentially a write to a static RAM,

with the static RAM controlling the wiper position. The response

from the WCR (current wiper position), to a Data Register is a

complete. The transfer can occur between the potentiometer and

one of its associated registers. The Read Status Register

instruction is the only unique format (see Figure 6 on page 7).

Two instructions require a two-byte sequence to complete (see

Figure 4 on page 7). These instructions transfer data between

the host and the X9110; either between the host and one of the

Data Registers or directly between the host and the Wiper

Counter Register. These instructions are:

1. XFR Data Register to Wiper Counter Register – This register

transfers the content of one specified Data Register to the

associated Wiper Counter Register.

2. XFR Wiper Counter Register to Data Register – This register

transfers the content of the specified Wiper Counter Register

to the specified associated Data Register.

See “Instruction Format” on page 8 for more details.

Write in Process (WIP bit)

The content of the Data Registers are saved to nonvolatile

memory when the CS pin goes from LOW to HIGH after a

complete write sequence is received by the device. The progress

of this internal write operation can be monitored by a Write In

Process (WIP) bit. The WIP bit is read with a Read Status

command (see Figure 6).

Power-Up and Power-Down Requirements

At all times, the V+ voltage must be greater than or equal to the

than or equal to the voltage at V-. During power-up and

1ms of each other.

I2

I1

I0

0

RB

RA

0

0

(MSB)

(LSB)

INSTRUCTION

OPCODE

REGISTER

SELECTION

RB

RA

REGISTER

0

0

1

1

0

1

0

1

DR0

DR1

DR2

DR3