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X9110 Datasheet(PDF) 5 Page - Renesas Technology Corp |
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X9110 Datasheet(HTML) 5 Page - Renesas Technology Corp |
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5 / 18 page ![]() X9110 FN8158 Rev 5.00 Page 5 of 18 October 28, 2016 At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within the individual array only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to select, and enable, one of 1024 switches. WIPER COUNTER REGISTER (WCR) The X9110 contains a Wiper Counter Register (see Table 1) for the XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of 1024 switches along its resistor array. The content of the WCR can be altered in one of three ways: (1) it may be written directly by the host via the write Wiper Counter Register instruction (serial load); (2) it may be written indirectly by transferring the content of one of four associated Data Registers via the XFR Data Register; (3) it is loaded with the content of its data register zero (DR0) upon power-up. The Wiper Counter Register is a volatile register; that is, its content is lost when the X9110 is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Power-up guidelines are recommended to ensure proper loadings of the DR0 value into the WCR. DATA REGISTERS (DR) The potentiometer has four 10-bit nonvolatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the Wiper Counter Register. All operations changing data in one of the Data Registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. DR[9:0] is used to store one of the 1024 wiper position (0~1023) (see Table 2). STATUS REGISTER (SR) This 1-bit status register is used to store the system status (see Table 3). WIP: Write In Progress status bit, read only. • When WIP = 1, indicates that high-voltage write cycle is in progress. • When WIP = 0, indicates that no high-voltage write cycle is in progress. TABLE 3. STATUS REGISTER, SR (1-BIT) TABLE 4. IDENTIFICATION BYTE FORMAT TABLE 1. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9–WCR0: Used to store the current wiper position (Volatile, V) WCR9 WCR8 WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0 VVVVVVVVVV (MSB) (LSB) TABLE 2. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: Used to store wiper positions or data (Nonvolatile, NV) BIT 9BIT 8BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0 NV NV NV NV NV NV NV NV NV NV (MSB) (LSB) WIP (LSB) ID3 ID2 ID1 ID0 0 0 A0 R/W 0101 (MSB) (LSB) DEVICE TYPE IDENTIFIER INTERNAL SLAVE ADDRESS READ OR WRITE BIT |
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