X9521 datasheet(4/24 Pages) RENESAS

4 / 24 page

X9521

FN8207 Rev 2.00

Page 4 of 24

September 21, 2010

DEVICE INTERNAL ADDRESSING

Addressing Protocol Overview

The user addressable internal components of the X9521

can be split up into three main parts:

—Two Digitally Controlled Potentiometers (DCPs)

—EEPROM array

—Control and Status (CONSTAT) Register

Depending upon the operation to be performed on each of

these individual parts, a 1, 2 or 3 Byte protocol is used. All

operations however must begin with the Slave Address

Byte being issued on the SDA pin. The Slave address

selects the part of the X9521 to be addressed, and speci-

fies if a Read or Write operation is to be performed.

It should be noted that in order to perform a write operation

to either a DCP or the EEPROM array, the Write Enable

Latch (WEL) bit must first be set (See “BL1, BL0: Block

Lock protection bits - (Nonvolatile)” on page 12.)

Slave Address Byte

Following a START condition, the master must output a

Slave Address Byte (Refer to Figure 4.). This byte consists

of three parts:

—The Device Type Identifier which consists of the most

significant four bits of the Slave Address (SA7 - SA4).

The Device Type Identifier must always be set to 1010 in

order to select the X9521.

—The next three bits (SA3 - SA1) are the Internal Device

Address bits. Setting these bits to 000 internally selects

the EEPROM array, while setting these bits to 111

selects the DCP structures in the X9521. The CONSTAT

Address 010.

—The Least Significant Bit of the Slave Address (SA0)

Byte is the R/W bit. This bit defines the operation to be

performed on the device being addressed (as defined in

the bits SA3 - SA1). When the R/W bit is “1”, then a

READ operation is selected. A “0” selects a WRITE oper-

ation (Refer to Figure 4.)

SCL

from

Master

Data Output

from

Transmitter

Data Output

from

Receiver

Start

Acknowledge

Figure 3.

Acknowledge Response From Receiver

SCL

from

Master

SA6

SA7

SA5

SA3 SA2

SA1

SA0

DEVICE TYPE

IDENTIFIER

READ /

SA4

Internal Address

(SA3 - SA1)

Internally Addressed

Device

000

EEPROM Array

010

CONSTAT Register

111

DCP

Bit SA0

Operation

0WRITE

READ

R/W

Figure 4.

Slave Address Format

101 0

WRITE

ADDRESS

INTERNAL

DEVICE

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