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X9521 Datasheet(PDF) 10 Page - Renesas Technology Corp

Part # X9521
Description  Dual DCP, EEPROM Memory Fiber Channel/Gigabit Ethernet Laser Diode Control for Fiber Optic Modules
PDF  24 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

X9521 Datasheet(HTML) 10 Page - Renesas Technology Corp

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X9521
FN8207 Rev 2.00
Page 10 of 24
September 21, 2010
EEPROM Array Read Operations
Read operations are initiated in the same manner as write
operations with the exception that the R/W bit of the Slave
Address Byte is set to one. There are three basic read
operations: Current EEPROM Address Read, Random
EEPROM Read, and Sequential EEPROM Read.
Current EEPROM Address Read
Internally the device contains an address counter that
maintains the address of the last word read incremented by
one. Therefore, if the last read was to address n, the next
read operation would access data from address n+1. On
power-up, the address of the address counter is undefined,
requiring a read or write operation for initialization.
Upon receipt of the Slave Address Byte with the R/W bit set
to one, the device issues an ACKNOWLEDGE and then
transmits the eight bits of the Data Byte. The master termi-
nates the read operation when it does not respond with an
ACKNOWLEDGE during the ninth clock and then issues a
STOP condition (See Figure 14 for the address,
ACKNOWLEDGE, and data transfer sequence).
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read opera-
tion, the master must either issue a STOP condition during
the ninth cycle or hold SDA HIGH during the ninth clock
cycle and then issue a STOP condition.
Another important point to note regarding the “Current
EEPROM Address Read” , is that this operation is not
available if the last executed operation was an access to a
DCP or the CONSTAT Register (i.e.: an operation using
the Device Type Identifier 1010111 or 1010010). Immedi-
ately after an operation to a DCP or CONSTAT Register is
performed, only a “Random EEPROM Read” is available.
Immediately following a “Random EEPROM Read” , a
“Current EEPROM Address Read” or “Sequential
EEPROM Read” is once again available (assuming that no
access to a DCP or CONSTAT Register occur in the
interim).
address
address
11
5 bytes
15
7 bytes
address
= 6
address pointer
ends here
Addr = 7
Figure 13. Example: Writing 12 bytes to a 16-byte page starting at location 11.
5 bytes
10
10
10
10
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
Figure 14. Current EEPROM Address Read Sequence
1 01 0 0 0 0



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