X9521 datasheet(12/24 Pages) RENESAS

12 / 24 page

X9521

FN8207 Rev 2.00

Page 12 of 24

September 21, 2010

CONTROL AND STATUS REGISTER

The Control and Status (CONSTAT) Register provides

the user with a mechanism for changing and reading

the status of various parameters of the X9521 (See

Figure 17).

The CONSTAT register is a combination of both volatile

and nonvolatile bits. The nonvolatile bits of the CONSTAT

ered down, then powered back up. The volatile bits how-

ever, will always power-up to a known logic state “0”

(irrespective of their value at power-down).

A detailed description of the function of each of the CON-

STAT register bits follows:

WEL: Write Enable Latch (Volatile)

The WEL bit controls the Write Enable status of the entire

X9521 device. This bit must first be enabled before ANY

write operation (to DCPs, EEPROM memory array, or the

CONSTAT register). If the WEL bit is not first enabled, then

ANY proceeding (volatile or nonvolatile) write operation to

DCPs, EEPROM array, as well as the CONSTAT register,

is aborted and no ACKNOWLEDGE is issued after a Data

Byte.

The WEL bit is a volatile latch that powers up in the dis-

abled, LOW (0) state. The WEL bit is enabled / set by writ-

ing 00000010 to the CONSTAT register. Once enabled,

the WEL bit remains set to “1” until either it is reset to “0”

(by writing 00000000 to the CONSTAT register) or until the

X9521 powers down, and then up again.

Writes to the WEL bit do not cause an internal high voltage

write cycle. Therefore, the device is ready for another oper-

ation immediately after a STOP condition is executed in the

CONSTAT Write command sequence (See Figure 18).

RWEL: Register Write Enable Latch (Volatile)

The RWEL bit controls the (CONSTAT) Register Write

Enable status of the X9521. Therefore, in order to write to

any of the bits of the CONSTAT Register (except WEL),

the RWEL bit must first be set to “1”. The RWEL bit is a vol-

atile bit that powers up in the disabled, LOW (“0”) state.

It must be noted that the RWEL bit can only be set, once

the WEL bit has first been enabled (See "CONSTAT Reg-

ister Write Operation").

The RWEL bit will reset itself to the default “0” state, in one

of three cases:

—After a successful write operation to any bits of the

CONSTAT register has been completed (See Figure

18).

—When the X9521 is powered down.

—When attempting to write to a Block Lock protected

region of the EEPROM memory (See "BL1, BL0: Block

Lock protection bits - (Nonvolatile)", below).

BL1, BL0: Block Lock protection bits - (Nonvolatile)

The Block Lock protection bits (BL1 and BL0) are used

to:

—Inhibit a write operation from being performed to certain

addresses of the EEPROM memory array

—Inhibit a DCP write operation (changing the “wiper posi-

tion”).

The region of EEPROM memory which is protected /

locked is determined by the combination of the BL1 and

BL0 bits written to the CONSTAT register. It is possible to

lock the regions of EEPROM memory shown in the table

below:

Bit(s)

Description

CS7 - CS5

Always “0”(RESERVED)

BL1 - BL0

Sets the Block Lock partition

RWEL

WEL

Write Enable Latch bit

CS0

Always “0” (RESERVED)

WEL

CS5

CS6

CS7

CS4

CS3

CS2

CS1

CS0

BL0

BL1

RWEL

Figure 17. CONSTAT Register Format

NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).

BL1 BL0

Protected Addresses

(Size)

Partition of array

locked

None (Default)

C0h - FFh (64 bytes)

Upper 1/4

80h - FFh (128 bytes)

Upper 1/2

00h - FFh (256 bytes)

All

X9521 Datasheet(PDF) 12 Page - Renesas Technology Corp

X9521 Datasheet(HTML) 12 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL