X9521 datasheet(9/24 Pages) RENESAS

9 / 24 page

X9521

FN8207 Rev 2.00

Page 9 of 24

September 21, 2010

2kbit EEPROM ARRAY

Operations on the 2kbit EEPROM Array, consist of either 1,

2 or 3 byte command sequences. All operations on the

EEPROM must begin with the Device Type Identifier of the

Slave Address set to 1010000. A Read or Write to the

EEPROM is selected by setting the LSB of the Slave

Address to the appropriate value R/W (Read = “1”, Write =

”0”).

In some cases when performing a Read or Write to the

EEPROM, an Address Byte may also need to be specified.

This Address Byte can contain the values 00h to FFh.

EEPROM Byte Write

In order to perform an EEPROM Byte Write operation to the

EEPROM array, the Write Enable Latch (WEL) bit of the

CONSTAT Register must first be set (See “BL1, BL0: Block

Lock protection bits - (Nonvolatile)” on page 12.)

For a write operation, the X9521 requires the Slave

Address Byte and an Address Byte. This gives the master

access to any one of the words in the array. After receipt of

the Address Byte, the X9521 responds with an

ACKNOWLEDGE, and awaits the next eight bits of data.

After receiving the 8 bits of the Data Byte, it again responds

with an ACKNOWLEDGE. The master then terminates the

transfer by generating a STOP condition, at which time the

X9521 begins the internal write cycle to the nonvolatile

memory (See Figure 12). During this internal write cycle,

the X9521 inputs are disabled, so it does not respond to

any requests from the master. The SDA output is at high

impedance. A write to a region of EEPROM memory which

has been protected with the Block-Lock feature (See “BL1,

BL0: Block Lock protection bits - (Nonvolatile)” on

page 12.), suppresses the ACKNOWLEDGE bit after the

Address Byte.

EEPROM Page Write

In order to perform an EEPROM Page Write operation to

the EEPROM array, the Write Enable Latch (WEL) bit of the

CONSTAT Register must first be set (See “BL1, BL0: Block

Lock protection bits - (Nonvolatile)” on page 12.)

The X9521 is capable of a page write operation. It is initi-

ated in the same manner as the byte write operation; but

instead of terminating the write cycle after the first data byte

is transferred, the master can transmit an unlimited number

of 8-bit bytes. After the receipt of each byte, the X9521

responds with an ACKNOWLEDGE, and the address is

internally incremented by one. The page address remains

constant. When the counter reaches the end of the page, it

“rolls over” and goes back to ‘0’ on the same page.

For example, if the master writes 12 bytes to the page start-

ing at location 11 (decimal), the first 5 bytes are written to

locations 11 through 15, while the last 7 bytes are written to

locations 0 through 6. Afterwards, the address counter

would point to location 7. If the master supplies more than

16 bytes of data, then new data overwrites the previous

data, one byte at a time (See Figure 13).

The master terminates the Data Byte loading by issuing a

STOP condition, which causes the X9521 to begin the non-

volatile write cycle. As with the byte write operation, all

inputs are disabled until completion of the internal write

cycle. See Figure 10 for the address, ACKNOWLEDGE,

and data transfer sequence.

Stops and EEPROM Write Modes

Stop conditions that terminate write operations must be

sent by the master after sending at least 1 full data byte

and receiving the subsequent ACKNOWLEDGE signal. If

the master issues a STOP within a Data Byte, or before the

X9521 issues a corresponding ACKNOWLEDGE, the

X9521 cancels the write operation. Therefore, the contents

of the EEPROM array does not change.

Slave

Address

Byte

Data

Byte

SDA Bus

Signals from

the Slave

Signals from

the Master

Figure 12. EEPROM Byte Write Sequence

Internal

Device

Address

1 01 0 0 0 0 0

WRITE Operation

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