FT28HC256 datasheet(6/23 Pages) FORCE

6 / 23 page

FT28HC256

Characteristics subject to change without notice.

6 of 23

REV 1.0

SOFTWARE ALGORITHM

Selecting the software data protection mode requires

the host system to precede data write operations by a

series of three write operations to three specific

addresses. Refer to Figure 6 and 7 for the sequence .

The three-byte sequence opens the page wr ite window,

enabling the host to write from one to one hundred

twenty-eight bytes of data. Once the page load cycle

has been completed, the device will automatically be

returned to the data protected state.

SOFTWARE DATA PROTECTION

Figure 6. Timing Sequence—Byte or Page Write

(VCC)

Write

Protected

VCC

Data

Address

AAA

5555

2AAA

5555

≤ tBLC MAX

Writes

Byte

Age

tWC

Figure 7. Write Sequence for Software Data

Protection

Regardless of whether the device has previously been

protected or not, once the software data protection

algorithm is used and data has been written, the

FT28HC256 will automatically disable further writes

unless another command is issued to cancel it. If no

further commands are issued the FT28HC256 will be

write protected during power-down and after any sub-

sequent power-up.

Note:

Once initiated, the sequence of write operations

should not be interrupted.

Write Last

Write Data XX

to Any

Write Data A0

to Address

5555

Write Data 55

to Address

2AAA

Write Data AA

to Address

5555

After tWC

Re-Enters Data

Protected State

Byte to

Last Address

Address

Optional

Byte/Page

Load Operation

Byte/Page

Load Enabled

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