FT28HC256 datasheet(5/23 Pages) FORCE

5 / 23 page

FT28HC256

Characteristics subject to change without notice.

5 of 23

REV 1.0

THE TOGGLE BIT I/O6

Figure 4. Toggle Bit Bus Sequence

Last

Write

I/O6

HIGH Z

VOH

VOL

Ready

* I/O6 Beginning and ending state of I/O6 will vary.

Figure 5. Toggle Bit Software Flow

The Toggle Bit can eliminate the chore of saving and

fetching the last address and data in order to implement

DATA Polling. This can be especially helpful in an array

comprised of multiple FT28HC256 memories that is

frequently updated. The timing diagram in Figure 4

illustrates the sequence of events on the bus. The soft-

ware flow diagram in Figure 5 illustrates a method for

polling the Toggle Bit.

HARDWARE DATA PROTECTION

The FT28HC256 provides two hardware features that

protect nonvolatile data from inadvertent writes.

– Default VCC Sense—All write functions are inhibited

when VCC is 3.5V typically.

– Write Inhibit—Holding either OE LOW, WE HIGH, or

CE HIGH will prevent an inadvertent write cycle during

power-up and power-down, maintaining data integrity.

SOFTWARE DATA PROTECTION

The FT28HC256 offers a softw are-controlled data pro-

tection feature. The FT28HC256 is shipped from FT

with the software data protection NOT ENABLED; that

is, the device will be in the standard operating mode. In

this mode data should be protected during power-up/

down oper ations through the use of e xternal circuits.

The host would then have open read and write access

of the device once VCC was stable.

The FT28HC256 can be automatically protected during

power-up and power-down (without the need for exter-

nal circuits) by employing the software data protection

feature. The internal software data protection circuit is

enabled after the first w ite operation, utilising the soft-

ware algor ithm. This circuit is non volatile, and will

remain set for the life of the device unless the reset

command is issued.

Once the software protection is enabled, the FT28HC256 is

also protected from inadvertent and accidental writes in the

powered-up state. That is, the software algorithm must be

issued prior to writing additional data to the device.

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FT28C256

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ok?

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Accum with

Addr n

Load Accum

From Addr n

Last Write

Ready

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