FT28HC256 datasheet(3/23 Pages) FORCE

3 / 23 page

FT28HC256

Characteristics subject to change without notice.

3 of 23

REV 1.0

DEVICE OPERATION

Read

Read operations are initiated by both OE and CE LOW.

The read operation is terminated by either CE or OE

returning HIGH. This two line control architecture elimi-

nates bus contention in a system environment. The

data bus will be in a high impedance state when either

OE or CE is HIGH.

Write

Write operations are initiated when both CE and WE

are LOW and OE is HIGH. The FT28HC256 suppor ts

both a CE and WE

WE, whiche ver occurs last. Similarly, the data is

latched internally by the rising edge of either CE or

WE, which ever occurs first A byte write operation,

once initiated, will automatically continue to comple-

tion, typically within 3ms.

Page Write Operation

The page write f eature of the FT28HC256 allows the

entire memory to be written in typically 0.8 seconds .

Page wr ite allows up to one hundred twenty-eight

bytes of data to be consecutively written to the

FT28HC256, prior to the commencement of the inter nal

programming cycle . The host can fetch data from

another device within the system during a page write

operation (change the source address), but the page

address (A 7 through A 14) f or each subsequent valid

write cycle to the part during this operation must be the

same as the initial page address.

The page write mode can be initiated dur ing any write

operation. Following the initial byte write cycle, the host

can write an additional one to one hundred twenty-

seven bytes in the same manner as the first byte was

written. Each successive byte load cycle , started b y

the WE HIGH to LO W tr ansition, m ust begin within

100µs of the falling edge of the preceding WE. If a sub-

sequent WE HIGH to LOW tr ansition is not detected

within 100µs , the internal automatic programming

cycle will commence . There is no page write window

limitation. Effectively the page write window is infinitel

wide, so long as the host continues to access the

device within the byte load cycle time of 100µs.

Write Operation Status Bits

The FT28HC256 provides the user two write operation

status bits. These can be used to optimised a system

write cycle time. The status bits are mapped onto the

I/O bus as shown in Figure 1.

Figure 1. Status Bit Assignment

DATA Polling (I/O7)

The FT28HC256 features DATA Polling as a method to

indicate to the host system that the byte write or page

write cycle has completed. DATA Polling allows a sim-

ple bit test operation to determine the status of the

FT28HC256. This eliminates additional interrupt inputs

or external hardware. During the internal programming

cycle, any attempt to read the last byte written will pro-

duce the complement of that data on I/O 7 (i.e., write

data = 0xxx xxxx, read data = 1xxx xxxx).

Once the

programming cycle is complete , I/O 7 will reflect true

data.

Toggle Bit (I/O6)

The FT28HC256 also provides another method for

determining when the internal write cycle is complete .

During the internal programming cycle I/O 6 will toggle

from HIGH to LO W and LOW to HIGH on subsequent

attempts to read the device. When the internal cycle is

complete the toggling will cease, and the device will be

accessible for additional read and write operations.

I/O

Reserved

Toggle Bit

DATA Polling

controlled write cycle. That is, the

address is latched b y the f alling edge of either CE

FT28HC256 Datasheet(PDF) 3 Page - Force Technologies Ltd

FT28HC256 Datasheet(HTML) 3 Page - Force Technologies Ltd

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Datasheet Download

Link URL