LPC83X datasheet(44/78 Pages) NXP

44 / 78 page

LPC83x

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Product data sheet

Rev. 1.2 — 4 April 2018

44 of 78

NXP Semiconductors

LPC83x

32-bit ARM Cortex-M0+ microcontroller

11.5 CoreMark data

Conditions: VDD = 3.3 V; Tamb = 25 °C; active mode; all peripherals except one UART and the

SCTimer/PWM disabled in the SYSAHBCLKCTRL register; BOD disabled; internal pull-up

resistors enabled. Measured with Keil uVision 5.10.

1 MHz - 6 MHz: external clock; IRC, PLL disabled.12 MHz: IRC enabled; PLL disabled. 24 MHz:

IRC enabled; PLL enabled.30 MHz: system oscillator enabled; PLL enabled.

Fig 22. CoreMark score

Conditions: VDD = 3.3 V; Tamb = 25 °C; active mode; all peripherals except one UART and the

SCTimer/PWM disabled in the SYSAHBCLKCTRL register; BOD disabled; internal pull-up

resistors enabled. Measured with Keil uVision 5.10.

1 MHz - 6 MHz: external clock; IRC, PLL disabled.12 MHz: IRC enabled; PLL disabled.24 MHz:

IRC enabled; PLL enabled.30 MHz: system oscillator enabled; PLL enabled.

Fig 23. Active mode: CoreMark power consumption IDD

aaa-014006

0.5

1.5

2.5

system clock frequency (MHz)

coremark score

((iterations/s)/MHz)

default

CPU/efficiency

low-current

CPU performance/efficiency

aaa-014007

system clock frequency (MHz)

IDD

(mA)

default

CPU/efficiency

low-current

CPU performance/efficiency

LPC83X Datasheet(PDF) 44 Page - NXP Semiconductors