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LPC83X Datasheet(PDF) 6 Page - NXP Semiconductors |
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LPC83X Datasheet(HTML) 6 Page - NXP Semiconductors |
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6 / 78 page ![]() LPC83x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 1.2 — 4 April 2018 6 of 78 NXP Semiconductors LPC83x 32-bit ARM Cortex-M0+ microcontroller 7. Pinning information 7.1 Pinning 7.2 Pin description The pin description table Table 3 shows the pin functions that are fixed to specific pins on each package. These fixed-pin functions are selectable through the switch matrix between GPIO and the ADC, SWD, RESET, and the XTAL pins. By default, the GPIO function is selected except on pins PIO0_2, PIO0_3, and PIO0_5. JTAG functions are available in boundary scan mode only. Fig 4. Pin configuration TSSOP20 package TSSOP20 PIO0_23/ADC_3 PIO0_14/ADC_2 PIO0_17/ADC_9 PIO0_0/TDO PIO0_13/ADC_10 VREFP PIO0_12 VREFN RESET/PIO0_5 VSS PIO0_4/ADC_11/WAKEUP/TRST VDD SWCLK/PIO0_3/TCK PIO0_8/XTALIN SWDIO/PIO0_2/TMS PIO0_9/XTALOUT PIO0_11/I2C0_SDA PIO0_1/CLKIN/TDI PIO0_10/I2C0_SCL PIO0_15 aaa-024129 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 Fig 5. Pin configuration HVQFN33 package aaa-024131 Transparent top view PIO0_9/XTALOUT SWDIO/PIO0_2/TMS PIO0_11/I2C0_SDA PIO0_8/XTALIN SWCLK/PIO0_3/TCK VDD PIO0_28/WKTCLKIN VREFN PIO0_4/ADC_11/TRST VREFP PIO0_5/RESET PIO0_7/ADC_0 PIO0_12 PIO0_6/ADC_1 PIO0_13/ADC_10 PIO0_0/TDO 8 17 7 18 6 19 5 20 421 3 22 2 23 1 24 terminal 1 index area 33 VSS |
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