–1

0–

REV. PrE

AD7680

PRELIMINARY TECHNICAL DATA

SERIAL INTERFACE

Figure 12 shows the detailed timing diagram for serial

interfacing to the AD7680. The serial clock provides the

conversion clock and also controls the transfer of informa-

tion from the AD7680 during conversion.

The

CS signal initiates the data transfer and conversion

process. The falling edge of

CS puts the track and hold

into hold mode, takes the bus out of tristate and the ana-

log input is sampled at this point.

The conversion is also

initiated at this point and will require at least 20 SCLK

cycles to complete. Once 17 SCLK falling edges have

elapsed, then the track and hold will go back into track on

the next SCLK rising edge. Figure 12 shows a 24 SCLK

transfer which allows for a 100kSPS throughput rate.

On

the 24th SCLK falling edge the SDATA line will go back

into tristate. If the rising edge of

CS occurs before 24

SCLKs have elapsed then the conversion will be termi-

nated and the SDATA line will go back into tri-state,

otherwise SDATA returns to tri-state on the 24th SCLK

falling edge as shown in Figure 12. A minimum of twenty

serial clock cycles are required to perform the conversion

process and to access data from the AD7680.

CS going

low provides the first leading zero to be read in by the

microcontroller or DSP. The remaining data is then

clocked out by subsequent SCLK falling edges beginning

with the 2nd leading zero, thus the first falling clock edge

on the serial clock has the first leading zero provided and

also clocks out the second leading zero. The data transfer

will consist of four leading zeros followed by the sixteen

bits of data followed by four trailing zeros, if a 24 SCLK

transfer is used as in Figure 12. The final bit ( 4th trailing

zero) in the data transfer is valid on the 24th falling edge,

having being clocked out on the previous (23rd) falling

edge. If a 20 SCLK transfer is used as shown in Figure

13, then the data output stream will only consist of four

leading zeros followed by sixteen bits of data with the final

bit valid on the 20th SCLK falling edge. A 20 SCLK

transfer will allow for a shorter cycle time and hence a

faster throughput rate to be achieved.

It is also possible to take valid data on each SCLK rising

edge rather than falling edge as the SCLK cycle time is

long enough to ensure the data is ready on the rising edge

of SCLK. However, the first leading zero will still be

driven by the

CS falling edge and so can only be taken on

the first SCLK falling edge. It may be ignored and the

first rising edge of SCLK after the

CS falling edge would

have the second leading zero provided and the 23rd rising

SCLK edge would have the final trailing zero provided.

This method may not work with most Micros/DSPs, but

could possibly be used with FPGAs and ASICs.

Figure 12. AD7680 Serial Interface Timing Diagram - 24 SCLK Transfer

Figure 13. AD7680 Serial Interface Timing Diagram - 20 SCLK Transfer

+5

SCLK

1

5

19

SDATA

3-STATE

2

34

3-STATE

DB0

18

ZERO

0

DB1

DB15

4 Leading Zeros

ZERO

ZERO

20

0

+5

SCLK

1

5

19

SDATA

3-STATE

2

34

22

3-STATE

DB0

18

ZERO

0

DB1

ZERO

21

4 Trailing Zeros

24

DB15

4 Leading Zeros

ZERO

ZERO

ZERO

ZERO

ZERO

23

20