ML60852 datasheet(21/81 Pages) OKI

21 / 81 page

PEDL60852-01

1Semiconductor

ML60852

21/81

(4) Receive packet ready interrupts (EP1, EP2, EP3, EP4 bulk, EP5 bulk)

These interrupts are generated when the respective EP has received an appropriate data packet from the USB

bus and the local MCU can read that data.

Operation

Source of operation

Description (conditions, responses, etc.)

Receive packet ready

interrupt generation

ML60852

The receive packet ready bit (D0) of the corresponding EP

status register (EPnSTAT) is asserted during data

reception when the EOP of the data packet has been

received and the data has been stored without error in the

corresponding FIFO. The end of a packet is recognized

when an EOP has arrived in the cases of both full packets

and short packets.

An interrupt is generated at this time, if the corresponding

receive packet ready interrupt enable bit has been

asserted.

(EOP: End of packet)

End of receive packet ready

interrupt

Local MCU (firmware) After the number of bytes in the receive FIFO data

(EPnFIFO) indicated by the corresponding receive byte

count register (EPnRXCNT) has been read, write a “1” into

the receive packet ready bit D0 of the corresponding EP

status register (EPnSTAT). (This status is reset when a “1”

is written in this bit.)

ML60852 Datasheet(PDF) 21 Page - OKI electronic componets