ML60852 datasheet(18/81 Pages) OKI

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PEDL60852-01

1Semiconductor

ML60852

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(2) At the time of reception, when an EOP is detected in the received data string, the ML608522 recognizes it as

the end of the received packet and asserts the receive packet ready status bit. The number of bytes in the

received packet is counted automatically by the receive byte count register (Note 1) corresponding to that end

point.

Note 1: Receive byte count register address: 58h to 5Dh and 74h to 75h.

(8) Interrupts

The ML60852 requests interrupts to the local MCU, etc., by asserting the -INTR pin. The interrupt causes are the

following:

(a) Setup ready for the 8-byte setup data

(b) EP0 receive packet ready

(d) EP1 transmit/receive packet ready

(e) EP2 transmit/receive packet ready

(f) EP3 transmit/receive packet ready

(g) EP4 transmit/receive packet ready

(h) EP5 transmit/receive packet ready

(i) SOF

(j) USB Bus reset assert

(k) USB Bus reset de-assert

(l) Suspend

(m) Awake

Although there is only one

INTR pin, the local MCU can identify the contents of the interrupt by reading out the

interrupt status register 1 (INTSTAT1) and the interrupt status register 2 (INTSTAT2). These interrupts can also be

masked dynamically by making individual settings in the interrupt enable register 1 (INTENBL1) and the interrupt

enable register 2 (INTENBL2).

The causes of the interrupts, their setting and resetting conditions, and the responses to them are described below.

The functions of the setup ready bit and the packet ready bit can, in some situations, be different from those

described here because of some special automatic operations done by the ML60852. Please see the descriptions of

the registers EP0STAT to EP5STAT for more details of such functions.

(1) Setup ready interrupt

Operation

Source of operation

Description (conditions, responses, etc.)

Setup ready

interrupt generation

ML60852

The setup ready bit (D2 of EP0STAT) is asserted when the

8-byte setup control data is received normally and has

been stored in the set of setup registers.

An interrupt is generated at this time if D1 of INTENBL1 has

been asserted.

→ The firmware can now read the set of setup registers.

End of setup ready interrupt Local MCU (firmware) After making the firmware read the 8-byte setup data, write

a “1” in bit D2 of EP0 status register (EP0STAT). This

causes the interrupt to be de-asserted.

The interrupt will not be de-asserted If a new 8-byte setup

data is received during this period. In this case, discard the

setup data that was being read at that time and read the

new 8-byte setup data.

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