ML60852 datasheet(26/81 Pages) OKI

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PEDL60852-01

1Semiconductor

ML60852

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(11) Operation of 2-layer structure FIFO during bulk transfer

The FIFOs of EP1 and EP2 have a 64 bytes x 2-layer structure. Also, when EP4 is assigned for bulk transfer, its

FIFO also has a 64-bytes x 2-layer structure. As a consequence, these FIFOs can temporarily store a maximum of

128 bytes of bulk transfer data.

(1) 2-Layer reception operation (“O” indicates the assert condition and “x” indicates de-assert condition)

In the case of 1

→2→3→4→5a→6

In the case of 1

→2→3→4→5b→6

Layer A

64 bytes

Layer B

64 bytes

Layer A

PKT

RDY

Layer B

PKT

RDY

EPn

receive

PKT

RDY

INTR

Start storing data in layer A of reception

Data of one packet has been stored.

Start reception and storing of data in

layer B.

Local MCU starts reading layer A.

When the storing of packet in layer B is

completed following the completion of

reading layer A.

When the reading of packet in layer A is

completed following the completion of

storing data in layer B.

xxx

From 5a: Layer A has become empty.

From 5b: Layer B has become full.

Starting reading layer B also.

• When one packet of receive data is stored in layer A of the FIFO and EOP is received, the ML60852 asserts the

packet ready bit of EPn and also asserts the

INTR pin. This makes it possible for the local MCU to read the

receive data.

• Subsequently, data can be received from the host, and the ML60852 switches the FIFO for storing to layer B.

• When one packet of data described above has been read from layer A of the FIFO, make the local MCU reset the

receive packet ready status of EPn (by writing a “1” into bit D0 of EPnSTAT).

• At the time the EPn receive packet ready status is reset, if the reception of layer B has not been completed, the

ML60852 resets the EPn receive packet ready status and de-asserts the

INTR pin.

• However, if the reception of layer B has been completed a the time the EPn receive packet ready status is reset,

the ML60852 rejects the request from the local MCU to reset the EPn receive packet ready status, and continues

to maintain the EPn receive packet ready status and the asserted condition of the

INTR pin.

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