SCD1284 datasheet(163/176 Pages) INTEL

163 / 176 page

IEEE 1284-Compatible Parallel Interface Controller — CD1284

Datasheet

163

8.3.2

Synchronous Timing

Use the following table as a reference to timing parameters of figures in this section.

Figure 27. Asynchronous DMA Write Cycle Timing

Figure 28. Asynchronous DMA Write Cycle Timing (Two Back-to-Back DMA Writes)

CLK

DMAACK*

DB[15:0]

MAY CHANGE

VALID

t19

t21

DMAREQ*

t24

NOTE: Figure 27 is still valid, however, Figure 28 illustrates more robust timing.

DB[15:0]

DMAACK*

CLK

NOTE: The data is sampled on the third rising edge of CLK following the assertion of DMAACK*. If DMAACK* is held

active for more than three CLK cycles then the next DMA write cycle will simply be delayed, but the data will still be

sampled on the third rising CLK edge following the assertion of DMAACK*. If DMAACK* is active for

< 3 CLKs, the

n the data is still sampled on the third rising CLK edge following the assertion of DMAACK* (provided that

DMAACK* is active long enough for the device to lastch it. Due to this somewhat synchronous behavior, care must

be taken to guarantee that the data is valid at this CLK edge. Do not assume that the data will be sampled on the

deassertion of DMAACK*.

t32

t29

VALID

DMAREQ*

t28

VALID

t31

t30

t32

t31

DMAACK* SYNCHRONIZED

HERE

DMAACK* SYNCHRONIZED

HERE

DATA SAMPLED

HERE

DATA SAMPLED

HERE

DMAACK* LATCHED

HERE

SEE NOTE

SCD1284 Datasheet(PDF) 163 Page - Intel Corporation

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