LTC2480CDD datasheet(22/40 Pages) LINER

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LTC2480

2480f

APPLICATIO S I FOR ATIO

Figure 7. External Serial Clock, CS = 0 Operation

External Serial Clock, 3-Wire I/O

This timing mode utilizes a 3-wire serial I/O interface. The

conversion result is shifted out of the device by an exter-

nally generated serial clock (SCK) signal, see Figure 7. CS

may be permanently tied to ground, simplifying the user

interface or transmission over an isolation barrier.

The external serial clock mode is selected at the end of the

power-on reset (POR) cycle. The POR cycle is concluded

typically 4ms after VCC exceedsapproximately2V.Thelevel

applied to SCK at this time determines if SCK is internal or

external. SCK must be driven LOW prior to the end of POR

in order to enter the external serial clock timing mode.

Since CS is tied LOW, the end-of-conversion (EOC) can be

continuously monitored at the SDO pin during the convert

and sleep states. EOC may be used as an interrupt to an

external controller indicating the conversion result is

ready. EOC = 1 while the conversion is in progress and

EOC = 0 once the conversion ends. On the falling edge of

EOC, the conversion result is loaded into an internal static

shift register. The input data is then shifted in via the SDI

pin on the rising edge of SCK (including the first rising

edge) and the output data is shifted out of the SDO pin on

each falling edge of SCK. EOC can be latched on the first

rising edge of SCK. On the 24th falling edge of SCK, SDO

goes HIGH (EOC = 1) indicating a new conversion has

begun. In applications where the processor generates 32

clock cycles, or to remain compatible with higher resolu-

tion converters, the LTC2480’s digital interface will ignore

extra clock edges seen during the next conversion period

after the 24th and outputs “1” for the extra clock cycles.

Internal Serial Clock, Single Cycle Operation

This timing mode uses an internal serial clock to shift out

the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 8.

In order to select the internal serial clock timing mode, the

serial clock pin (SCK) must be floating (Hi-Z) or pulled

HIGH prior to the falling edge of CS. The device will not

enter the internal serial clock mode if SCK is driven LOW

on the falling edge of CS. An internal weak pull-up resistor

is active on the SCK pin during the falling edge of CS;

therefore, the internal serial clock timing mode is auto-

matically selected if SCK is not externally driven.

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

Once CS is pulled LOW, SCK goes LOW and EOC is output

to the SDO pin. EOC = 1 while a conversion is in progress

and EOC = 0 if the device is in the sleep state.

GS2

GS1

GS0

SPD

SDI*

DON’T CARE

EOC

BIT 23

SDO

SCK

(EXTERNAL)

MSB

SIG

BIT 0

LSB

BIT 4

BIT 19

BIT 18

BIT 17

BIT 16

BIT 20

BIT 21

BIT 22

DATA OUTPUT

CONVERSION

2480 F07

CONVERSION

VCC

VREF

IN+

IN–

SCK

SDI

SDO

GND

210

INT/EXT CLOCK

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG

INPUT

µF

2.7V TO 5.5V

LTC2480

3-WIRE

SPI INTERFACE

LTC2480CDD Datasheet(PDF) 22 Page - Linear Technology

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