LTC2480CDD datasheet(29/40 Pages) LINER

29 / 40 page

LTC2480

2480f

Reference Current

In a similar fashion, the LTC2480 samples the differential

reference pins VREF+ and GND transferring small amount

of charge to and from the external driving circuits thus

producing a dynamic reference current. This current does

not change the converter offset, but it may degrade the

gain and INL performance. The effect of this current can be

analyzed in two distinct situations.

For relatively small values of the external reference capaci-

tors (CREF < 1nF), the voltage on the sampling capacitor

settles almost completely and relatively large values for

the source impedance result in only small errors. Such

values for CREF will deteriorate the converter offset and

gain performance without significant benefits of reference

filtering and the user is advised to avoid them.

Larger values of reference capacitors (CREF > 1nF) may be

required as reference filters in certain configurations.

Such capacitors will average the reference sampling charge

and the external source resistance will see a quasi con-

stant reference differential impedance.

In the following discussion, it is assumed the input and

reference common mode are the same. Using internal

oscillator for 60Hz mode, the typical differential refer-

ence resistance is 1M

Ω which generates a full-scale

(VREF/2) gain error of 0.51ppm for each ohm of source

resistance driving the VREF pin. For 50Hz/60Hz mode, the

related difference resistance is 1.1M

Ω and the resulting

full-scale error is 0.46ppm for each ohm of source

resistance driving the VREF pin. For 50Hz mode, the

related difference resistance is 1.2M

Ω and the resulting

full-scale error is 0.42ppm for each ohm of source

resistance driving the VREF pin. When FO is driven by an

external oscillator with a frequency fEOSC (external con-

version clock operation), the typical differential reference

resistance is 0.30 • 1012/fEOSC Ω and each ohm of source

resistance driving the VREF pin will result in 1.67 • 10–6 •

fEOSCppm gain error. The typical +FS and –FS errors for

various combinations of source resistance seen by the

VREF pin and external capacitance connected to that pin

are shown in Figures 15-18.

In addition to this gain error, the converter INL perfor-

mance is degraded by the reference source impedance.

The INL is caused by the input dependent terms

–VIN2/(VREF • REQ) – (0.5 • VREF • DT)/REQ in the reference

pin current as expressed in Figure 11. When using internal

oscillator and 60Hz mode, every 100

Ω of reference source

resistance translates into about 0.67ppm additional INL

error. When using internal oscillator and 50Hz/60Hz mode,

every 100

Ω of reference source resistance translates into

about 0.61ppm additional INL error. When using internal

oscillator and 50Hz mode, every 100

Ω of reference source

resistance translates into about 0.56ppm additional INL

error. When FO is driven by an external oscillator with a

frequency fEOSC, every 100Ω of source resistance driving

VREF translates into about 2.18 • 10–6 • fEOSCppm addi-

tional INL error. Figure 19 shows the typical INL error due

to the source resistance driving the VREF pin when large

CREF values are used. The user is advised to minimize the

source impedance driving the VREF pin.

In applications where the reference and input common

mode voltages are different, extra errors are introduced.

For every 1V of the reference and input common mode

voltage difference (VREFCM – VINCM) and a 5V reference,

each Ohm of reference source resistance introduces an

extra (VREFCM – VINCM)/(VREF • REQ) full-scale gain error,

which is 0.074ppm when using internal oscillator and

60Hz mode. When using internal oscillator and 50Hz/60Hz

mode, the extra full-scale gain error is 0.067ppm. When

using internal oscillator and 50Hz mode, the extra gain

error is 0.061ppm. If an external clock is used, the corre-

sponding extra gain error is 0.24 • 10–6 • fEOSCppm.

The magnitude of the dynamic reference current depends

upon the size of the very stable internal sampling capaci-

tors and upon the accuracy of the converter sampling

clock. The accuracy of the internal clock over the entire

temperature and power supply range is typically better

than 0.5%. Such a specification can also be easily achieved

by an external clock. When relatively stable resistors

(50ppm/

°C) are used for the external source impedance

seen by VREF+ and GND, the expected drift of the dynamic

current gain error will be insignificant (about 1% of its

value over the entire temperature and voltage range). Even

for the most stringent applications a one-time calibration

operation may be sufficient.

In addition to the reference sampling charge, the reference

pins ESD protection diodes have a temperature dependent

APPLICATIO S I FOR ATIO

LTC2480CDD Datasheet(PDF) 29 Page - Linear Technology

LTC2480CDD Datasheet(HTML) 29 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL