LT3486 datasheet(14/20 Pages) LINER

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LT3486

3486f

S I FOR ATIO

APPLICATIO

Figure 10. Recommended Layout for LT3486

the ﬁgure. A PWM logic input is applied to the gate of the

NMOS and the PWM pin of the LT3486. When the PWM

input is taken high, the LEDs are connected to the RFB

resistor and a current ILED = 200mV/RFB ﬂows through

the LEDs. When the PWM input is taken low, the LEDs are

disconnected and turn off. The low PWM input applied to

the LT3486 ensures that the respective converter turns

off and its VC pin goes high impedance. This ensures that

the capacitor connected to the VC pin retains its voltage

which in turn allows the LEDs to turn on faster, as shown

in Figure 8(b). The CTRL pin is not used to modulate the

LED current in the scheme. It can be connected to a supply

voltage greater than 1.8V.

The dimming control pins (PWM1, PWM2) can be used

to extend the dimming range for the individual switching

converters. The LED current can be controlled down to

µA levels by feeding a PWM signal with frequencies in the

range of 80Hz to 50kHz. The LED current can be controlled

by PWM frequencies above 50kHz but the controllable

current decreases with increasing frequency. Pulling the

PWM pins below 0.4V disables the respective switcher.

Taking it higher than 0.9V resumes normal operation.

Connect these pins to 0.9V or higher if not in use.

Figure 9 shows the LED current variation vs PWM duty

cycle. The LED current is controlled by applying a PWM

of frequency 100Hz, 1kHz and 25kHz to the circuit of

Figure 8a. As seen in the curves, the LED string is able to

get a wide (1000:1) dimming range with PWM frequency of

100Hz. The dimming range decreases as PWM frequency

goes up.

Board Layout Consideration

As with all switching regulators, careful attention must be

paid to the PCB board layout and component placement.

To prevent electromagnetic interference (EMI) problems,

proper layout of high frequency switching paths is essential.

Minimize the length and area of all traces connected to the

switching node pins (SW1 and SW2). Keep the feedback

pins (FB1 and FB2) away from the switching nodes.

The DFN and FE packages both have an exposed paddle

that must be connected to the system ground. The ground

connection for the feedback resistors should be tied directly

to the ground plane and not shared with any other compo-

nent, except the RT resistor, ensuring a clean, noise-free

connection. Recommended component placement for the

DFN package is shown in the Figure 10.

Figure 9. LED Current Variation vs PWM Duty Cycle

PWM DUTY CYCLE (%)

0.1

100

0.01

100

3486 F09

0.01

0.1

PWM FREQ = 100Hz

PWM FREQ = 1kHz

PWM FREQ = 25kHz

3486 F10

OVP1

VOUT1

VOUT2

FB1

FB2

LED1

LED2

CTRL1

CTRL2

VIN

SW1

SW2

VIN

VC1

PWM1

REF

OVP2

SHDN

VC2

PWM2

VIAs TO VIN PLANE

VIAs TO GROUND PLANE

VIAs TO VIN PLANE

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