TE28F320B3BC90 datasheet(12/58 Pages) INTEL

12 / 58 page

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

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Table 2.

3 Volt Advanced Boot Block Pin Descriptions

Symbol

Type

Name and Function

A0–A21

INPUT

ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or

erase cycle.

28F004B3: A[0-18], 28F008B3: A[0-19], 28F016B3: A[0-20],

28F400B3: A[0-17], 28F800B3: A[0-18], 28F160B3: A[0-19],

28F320B3: A[0-20], 28F640B3: A[0-21]

DQ0–DQ7

INPUT/

OUTPUT

DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program

command. Inputs commands to the Command User Interface when CE# and WE# are active. Data is

internally latched. Outputs array, identifier and status register data. The data pins float to tri-state when

the chip is de-selected or the outputs are disabled.

DQ8–

DQ15

INPUT/

OUTPUT

DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program

command. Data is internally latched. Outputs array and identifier data. The data pins float to tri-state

when the chip is de-selected. Not included on x8 products.

CE#

INPUT

CHIP ENABLE: Activates the internal control logic, input buffers, decoders and sense amplifiers. CE#

is active low. CE# high de-selects the memory device and reduces power consumption to standby

levels.

OE#

INPUT

OUTPUT ENABLE: Enables the device’s outputs through the data buffers during a read operation.

OE# is active low.

WE#

INPUT

WRITE ENABLE: Controls writes to the Command Register and memory array. WE# is active low.

Addresses and data are latched on the rising edge of the second WE# pulse.

RP#

INPUT

RESET/DEEP POWER-DOWN: Uses two voltage levels (VIL, VIH) to control reset/deep power-down

mode.

When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs

to High-Z, resets the Write State Machine, and minimizes current levels (ICCD).

When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-

low to logic-high, the device defaults to the read array mode.

WP#

INPUT

WRITE PROTECT: Provides a method for locking and unlocking the two lockable parameter blocks.

When WP# is at logic low, the lockable blocks are locked, preventing program and erase

operations to those blocks. If a program or erase operation is attempted on a locked block, SR.1 and

either SR.4 [program] or SR.5 [erase] will be set to indicate the operation failed.

When WP# is at logic high, the lockable blocks are unlocked and can be programmed or erased.

See Section 3.3 for details on write protection.

VCCQ

INPUT

OUTPUT VCC: Enables all outputs to be driven to 1.8 V – 2.5 V while the VCC is at 2.7 V–3.3 V. If the

VCC is regulated to 2.7 V–2.85 V, VCCQ can be driven at 1.65 V–2.5 V to achieve lowest power

operation (see Section 4.4

This input may be tied directly to VCC (2.7 V–3.6 V).

VCC

DEVICE POWER SUPPLY: 2.7 V–3.6 V

VPP

PROGRAM/ERASE POWER SUPPLY: Supplies power for program and erase operations. VPP may

be the same as VCC (2.7 V–3.6 V) for single supply voltage operation. For fast programming at

manufacturing, 11.4 V–12.6 V may be supplied to VPP. This pin cannot be left floating. Applying

11.4 V–12.6 V to VPP can only be done for a maximum of 1000 cycles on the main blocks and 2500

cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum (see

Section 3.4 for details).

VPP < VPPLK protects memory contents against inadvertent or unintended program and erase

commands.

GND

GROUND: For all internal circuitry. All ground inputs must be connected.

NO CONNECT: Pin may be driven or left floating.

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